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Data sheet acquired from Harris Semiconductor
SCHS118
August 1997
CD54HC08, CD54HCT08,
CD74HC08, CD74HCT08
High Speed CMOS Logic
Features
Description
• Buffered Inputs
[ /Title
(CD54H
Typical Propagation Delay:
CL = 15pF, TA = 25oC
7ns
at
VCC
=
5V,
C08,
• Fanout (Over Temperature Range)
CD54H
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
CwwTw0.D8a,taSheet4U.-coBmus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74H
• Wide Operating Temperature Range . . . -55oC to 125oC
C08,
CD74H
CT08)
/Sub-
ject
(High
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH
The Harris CD54HC08, CD54HCT08, CD74HC08 and
CD74HCT08 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG.
NO.
CD74HC08E
-55 to 125 14 Ld PDIP
E14.3
CD74HCT08E
-55 to 125 14 Ld PDIP
E14.3
CD74HC08M
-55 to 125 14 Ld SOIC
M14.15
CD74HCT08M
-55 to 125 14 Ld SOIC
M14.15
CD54HC08F
-55 to 125 14 Ld CERDIP F14.3
CD54HCT08F
-55 to 125 14 Ld CERDIP F14.3
CD54HC08W
-55 to 125 Wafer
CD54HCT08W
-55 to 125 Wafer
CD54HC08H
-55 to 125 Die
CD54HCT80H
-55 to 125 Die
NOTE:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
Pinout
CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
(PDIP, CERDIP, SOIC)
TOP VIEW
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1549.1

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CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
Functional Diagram
www.DataSheet4U.com
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
14
VCC
13
4B
12
4A
11
4Y
10
3B
9
3A
8
3Y
HC Logic Symbol
nA
nB
TRUTH TABLE
INPUTS
OUTPUT
nA nB nY
L LL
L HL
H LL
H HH
NOTE: H = High Voltage Level, L = Low Voltage Level
HCT Logic Symbol
nA
nY
nB
nY
2

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CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
www.DataSheet4DUC.cIonmput or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 100
N/A
CERDIP Package . . . . . . . . . . . . . . . . 130
55
SOIC Package . . . . . . . . . . . . . . . . . . . 180
N/A
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
SYMBOL
TEST
CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH -
-
VIL - -
VOH
VOL
II
VIH or
VIL
VIH or
VIL
VCC or
GND
-0.02
-0.02
-0.02
-
-4
-5.2
0.02
0.02
0.02
-
4
5.2
-
2 1.5 - -
4.5 3.15 -
-
6 4.2 - -
2 - - 0.5
4.5 - - 1.35
6 - - 1.8
2 1.9 - -
4.5 4.4 -
-
6 5.9 - -
- ---
4.5 3.98 -
-
6 5.48 -
-
2 - - 0.1
4.5 - - 0.1
6 - - 0.1
- ---
4.5 - - 0.26
6 - - 0.26
6 - - ±0.1
-40oC TO 85oC
MIN MAX
1.5 -
3.15 -
4.2 -
- 0.5
- 1.35
- 1.8
1.9 -
4.4 -
5.9 -
--
3.84 -
5.34 -
- 0.1
- 0.1
- 0.1
--
- 0.33
- 0.33
- ±1
-55oC TO 125oC
MIN MAX UNITS
1.5 - V
3.15 -
V
4.2 - V
- 0.5 V
- 1.35 V
- 1.8 V
1.9 - V
4.4 - V
5.9 - V
- -V
3.7 - V
5.2 - V
- 0.1 V
- 0.1 V
- 0.1 V
- -V
- 0.4 V
- 0.4 V
- ±1 µA
3

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CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
DC Electrical Specifications (Continued)
TEST
CONDITIONS
25oC
-40oC TO 85oC
PARAMETER
Quiescent Device
Current
SYMBOL
ICC
VI (V)
VCC or
GND
IO (mA) VCC (V)
06
MIN
-
TYP MAX
-2
MIN
-
MAX
20
HCT TYPES
High Level Input
Voltage
VIH -
- 4.5 to 2 - -
5.5
2
-
Low Level Input
Voltage
VIL
-
- 4.5 to - - 0.8 -
0.8
5.5
High Level Output
Voltage
www.DataSheet4UC.McoOmS Loads
VOH VIH or -0.02 4.5 4.4 - - 4.4
VIL
-
High Level Output
Voltage
TTL Loads
-4
4.5 3.98 -
- 3.84
-
Low Level Output
Voltage
CMOS Loads
VOL VIH or 0.02
4.5
-
- 0.1
-
VIL
0.1
Low Level Output
Voltage
TTL Loads
4
4.5
-
- 0.26
-
0.33
Input Leakage
Current
II
VCC
0
5.5 -
and
GND
±0.1 -
±1
Quiescent Device
Current
ICC VCC or 0
GND
5.5 - - 2
-
20
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)
ICC
VCC
- 2.1
- 4.5 to - 100 360 -
5.5
450
NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
-55oC TO 125oC
MIN MAX UNITS
- 40 µA
2 -V
- 0.8 V
4.4 - V
3.7 - V
- 0.1 V
- 0.4 V
- ±1 µA
- 40 µA
- 490 µA
INPUT
UNIT LOADS
All 0.6
NOTE: Unit Load is
Specifications table,
e.IgC.C3l6im0µitAspmeacxifieadt 2in5oDCC.
Electrical
Switching Specifications Input tr, tf = 6ns
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
TEST
VCC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
tPLH, tPHL CL = 50pF
2 - - 90 - 115 - 135 ns
4.5 -
- 18
-
23
-
27 ns
6 - - 15
-
20
-
23 ns
Propagation Delay, Data Input to tPLH, tPHL CL = 15pF
5 -7 -
-
-
-
- ns
Output Y
4

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CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Transition Times (Figure 1)
tTLH, tTHL CL = 50pF
2 - - 75
-
95
- 110 ns
4.5 -
- 15
-
19
-
22 ns
6 - - 13
-
16
-
19 ns
Input Capacitance
Power Dissipation Capacitance
(Note 3, 4)
CI
CPD
-
- - - 10
-
10
-
10 pF
-
5 - 37 -
-
-
-
- pF
HCT TYPES
Propagation Delay, Input to
tPLH, tPHL CL = 50pF
4.5 -
- 25
-
31
-
38 ns
www.DataSheet4UO.uctopmut Y (Figure 2)
Propagation Delay, Data Input to tPLH, tPHL CL = 15pF
5 - 10 -
-
-
-
- ns
Output Y
Transition Times (Figure 2)
tTLH, tTHL CL = 50pF
4.5 -
- 15
-
19
-
22 ns
Input Capacitance
CI CL = 50pF
- - - 10
-
10
-
10 pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5 - 51 -
-
-
-
- pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
2.7V
1.3V
0.3V
tf = 6ns
3V
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
1.3V
10%
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5