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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C80F7/C80F9/C80G7/C80G9 Microcontroller
The S3C80F7/C80F9/C80G7/C80G9 single-chip CMOS microcontroller is fabricated using a highly advanced
CMOS process and is based on Samsung's newest CPU architecture.
The S3C80F9/C80G9 is the microcontroller which has 32-Kbyte mask-programmable ROM and S3C80F7/C80G7
is the microcontroller which has 24-Kbyte mask-programmable ROM.
The S3P80F9/P80G9 is the microcontroller which has 32-Kbyte one-time-programmable EPROM and
S3P80F7/P80G7 is the microcontroller which has 24-Kbyte one-time-programmable EPROM.
Using a proven modular design approach, Samsung engineers developed S3C80F7/C80F9/C80G7/C80G9 by
integrating the following peripheral modules with the powerful SAM87 RC core:
— Internal LVD circuit and 16 bit-programmable pins for external interrupts.
— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
— One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.
— One 8-bit counter with auto-reload function and one-shot or repeat control.
The S3C80F7/C80F9/C80G7/C80G9 is a versatile general-purpose microcontroller which is especially suitable
for use as remote transmitter controller. It is currently available in a 32-pin SOP, 42-pin SDIP and 44-pin QFP
package.
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PRODUCT OVERVIEW
S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)
FEATURES
CPU
SAM87RC CPU core
Memory
32-Kbyte internal ROM (S3C80F9/C80G9)
: 0000H–7FFFH
24-Kbyte internal ROM (S3C80F7/C80G7)
: 0000H–5FFFH
Data memory: 272-byte RAM (318 register)
Instruction Set
78 instructions
IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
500 ns at 8-MHz fOSC (minimum)
Interrupts
22 interrupt sources with 16 vector and 7 level.
I/O Ports
Three 8-bit I/O ports (P0–P2), one 8-bit output
port(P4) and 6-bit port (P3) for a total of 38 bit-
programmable pins.(44-QFP)
Three 8-bit I/O ports (P0–P2), one 8-bit output
port(P4) and 4-bit port (P3) for a total of 36 bit-
programmable pins.(42-SDIP)
Three 8-bit I/O ports (P0–P2) and one 2-bit I/O
port (P3) for a total of 26-bit programmable pins.
(32-SOP)
Timers and Timer/Counters
One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function
One 8-bit timer/counter (Timer 0) with three
operating modes; Interval mode, Capture and
PWM mode.
One 16-bit timer/counter (Timer1) with two
operating modes; Interval mode and Capture.
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Carrier Frequency Generator
One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)
Back-up mode
When VDD is lower than VLVD, the chip enters
Back-up mode to block oscillation and reduce
the current consumption.
In S3C80G7/C80G9, this function is disabled
when operating state is “STOP mode”.
When RESET pin is lower than Input Low
Voltage (VIL), the chip enters Back-up mode to
block oscillation and reduce the current
consumption.
Low Voltage Detect Circuit
Low voltage detect to get into Back-up mode.
Low level detect voltage
S3C80F7/C80F9: 2.20 V (Typ) ± 200mV
S3C80G7/C80G9: 1.90 V (Typ) ± 200mV
Operating Temperature Range
–40 °C to + 85 °C
Operating Voltage Range
1.7V to 5.0V at 4 MHz fOSC (S3C80G7/C80G9)
2.0V to 5.0V at 8 MHz fOSC (S3C80F7/C80F9)
Package Type
44-pin QFP-1010B
42-pin SDIP
32-pin SOP

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)
BLOCK DIAGRAM
PRODUCT OVERVIEW
P0.0-0.3 (INT0-INT3)
P0.4-P0.7 (INT4)
P1.0-P1.7
XIN
XOUT
VDD LVD
Port 0
Port 1
MAIN
OSC
8-Bit
Basic
Timer
8-Bit
Timer/
Counter
16-Bit
Timer/
Counter
I/O Port and Interrupt
Control
SAM87RC
CPU
32K-Bytes
ROM
317-Bytes
Register
File
TEST
RESET
Port 2
Port 3
P2.0-2.3 (INT5-INT8)
P2.4-2.7 (INT9)
P3.0-T0PWM/
T0CAP/(T1CAP)
P3.1-REM/(T0CK)
P3.2/(T0CK)
P3.3/(T1CAP)
P3.4-3.5
Port 4
P4.0-4.7
Carrier
Registor
(Counter A)
Figure 1-1. Block Diagram
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PRODUCT OVERVIEW
PIN ASSIGNMENTS
S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)
P4.2
P4.1
P4.0
P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P2.4/INT9
P3.0/T0PWM/T0CAP/SDAT
R3.1/REM/SCLK
VDD
VSS
XOUT
XIN
TEST
P2.5/INT9
P2.6/INT9
RESET
P2.7/INT9
P1.0
P3.2/T0CK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 P4.3
41 P0.7/INT4
40 P0.6/INT4
39 P0.5/INT4
38 P0.4/INT4
37 P0.3/INT3
36 P0.2/INT2
S3C80F7/C80F9
/C80G7/C80G9
35
34
33
P0.1/INT1
P0.0/INT0
P4.4
(Top View)
32 P4.5
31 P4.6
42-SDIP
30 P1.7
29 P1.6
28 P1.5
27 P1.4
26 P1.3
25 P1.2
24 P1.1
23 P4.7
22 P3.3/T1CAP
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)
PRODUCT OVERVIEW
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4
P4.3
P4.2
P4.1
P4.0
P2.0/INT5
P2.1/INT6
P2.2/INT7
34 22
35 21
36 S3C80F7/C80F9 20
37
38
/C80G7/C80G9
19
18
39 (Top View) 17
40 16
41 15
42 (44-QFP) 14
43 13
44 12
P1.3
P1.2
P1.1
P4.7
P3.3/T1CAP
P3.2/T0CK
P1.0
P2.7/INT9
P3.5
P3.4
RESET
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
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