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® STB5600
GPS RF FRONT-END IC
s ONE CHIP SYSTEM TO INTERFACE
ACTIVE ANTENNA TO ST20GP1
MICROCONTROLLER
s COMPLETE RECEIVER USING NOVEL
DUAL CONVERSION ARCHITECTURE WITH
SINGLE IF FILTER
s MINIMUM EXTERNAL COMPONENTS
s COMPATIBLE WITH GPS L1 SPS SIGNAL
s INTERNALLY STABILISED POWER RAILS
s CMOS OUTPUT LEVELS
s FROM 3.3 TO 5.9V SUPPLY VOLTAGE
s TQFP32 PACKAGE
DESCRIPTION
The STB5600, using STMicroelectronics HSB2,
High Speed Bipolar technology, implements a
Global Positioning System RF front-end.
The chip provides down conversion from thDe aGtaPSSheet4U.com
(L1) signal at 1575 MHz via an IF of 20MHz to an
output frequency of 4MHz suitable for ST20GP1
GPS processor.
It uses a single external reference oscillator to
generate both RF local oscillator signals and the
processor reference clock.
TQFP32
MARKING:
STB5600
TRACEAB. CODE
ASSY CODE
PIN CONNECTION (top view)
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August 1998
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STB5600
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FUNCTIONAL DESCRIPTION
The STB5600 GPS front-end is fed with the signal from an active antenna, via a ceramic RF filter. The
gain between the antenna element and the STB5600 is expected to be between 10dB and 35dB
overall, made up of the antenna LNA gain, the feeder loss, connector loss, and the ceramic filter loss.
In order to use an off-the-shelf ceramic filter, conventionally 50 Ohms single ended, a matching circuit is
used. (see appendix A.1), which provides a 300 Ohm differential drive to the STB5600. A similar circuit
can be used to feed the LO signal if using the recommended low-cost oscillator circuit (appendix A.3).
Note that the STB5600 radio architecture and the oscillator described here are covered by various
patents held by SGS-Thomson and by others. The use of the circuits described in this data-sheet for any
other purpose may infringe such patents.
- RF SECTION
The differential input signal is amplified by the RF-Amp and mixed with the oscillator signal amplified
from the LO+,LO- inputs to generate a balanced 20.46MHz IF signal. The LO buffer amplifier may be
fed differential or single ended signals, at levels between -60dBm and -20dBm .
- IF SECTION
The 20MHz differential signal from the mixer is fed through an external LC filter to suppress undesirable
signals and mixer products. The multi-stage high-sensitivity limiting amplifier is connected to a D-type
latch clocked by an internally derived 16MHz clock.. The effect of sampling the 20MHz signal at 16MHz
is to create a sub-sampling alias at 4MHz. This is fed to the output level-converters.
- DIVIDER SECTION
The 80MHz oscillator signal may be provided single-ended or differentially to the high impedance
80MHz+, 80MHz- inputs. Any unused inpuDtsatsahSohueldetb4eU.ccoonmnected to GNDLOGIC via a 1nF capacitor.
The 80MHz signal is amplified, then divided by 5 to create the 16.368MHz clock required by the
ST20GP1 processor, also used to clock the output latch of the STB5600.
- OUTPUT SECTION
The output latch samples the 20.46MHz intermediate frequency at a 16.368MHz rate, performing the
dual function of second downconversion and latching. The downconversion occurs by sub-sampling
aliasing, such that the digital output represents a 4.096MHz centre frequency
The output buffers perform level translation from the internal ECL levels to CMOS compatible outputs
referred to external ground.
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ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VCC DC Supply Voltage
RF+, RF- RF Input
Tj Junct ion Temperature
Tstg St orage Temperature Range
Rthj-a mb Thermal Resistance Junction-ambient
Value
5.9
8
150
-40 to 125
80
Uni t
V
dB m
oC
oC
o C /W
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PIN CONFIGURATION
Apply 5V at the CE, VCCRF, VCCIF, VCCLOGIC pins, apply 3 V at the VCCDRIVE
Pin
Symbol
Typ. DC Bias
Dexription
1 IF1+
3.6 V
Mixer O utput 1
2 IF 1-
3.6 V
Mixer O utput 2
3 V CCRF
4 RF+
5V
3.5 V
RF Power Supply
RF Input
5 RF-
3.5 V
RF Input
6 V CCRF
5V
RF Power Supply
7 VEERF
2 V RF Voltage Reference
8 GNDRF
0V
RF Ground
9 V CCRF
5V
RF Power Supply
10 LO+
3.5 V
Local Oscillator Input
11 LO-
3.5 V
Local Oscillator Input
12 V CCRF
5V
RF Power Supply
13 VCCLOGIC
5V
Logic Power Supply
14 80 MHz+
4V
80 MHz Clock Input
15 80 MHz-
4V
80 MHz Clock Input
16 VCCLOGIC
5V
Logic Power Supply
17 VEELOGIC
2 V Logic Voltage Reference
18 CLOCK+ 0.3 V or 3 V Da1t6aMShHezeCt4loUc.kcoCmMOS Output
19 Not Connected
20 GNDDRIVE
0V
CMO S Drive Ground
21
DATA
0.3 V or 3 V
4 MHz Data CMOS Output
22 GNDDRIVE
0V
CMO S Drive Ground
23 VCCDRIVE
3 V CMOS Drive Power Supply
24 CE
3V
Chip Enable
25 G ND 0 V Substrate Ground
26 GNDLOGIC
0V
Logic G round
27 GNDIF
0V
IF Ground
28 VEEIF
2 V IF Voltage Reference
29 VCCIF
5V
IF Power Supply
30 IF 2-
4 V Limiting Amplifier Input
31 IF2+
4 V Limiting Amplifier Input
32 VCCIF
5V
IF Power Supply
Extern al circuit
see application circuit
see application circuit
100 nF t o VEERF
AC Coupled
AC Coupled
100 nF to VEERF
100 nF to VCCRF
100 nF to VEERF
AC Coupled
AC Coupled
100 nF to VEERF
100 nF to VEELOGIC
AC Coupled
AC Coupled
100 nF to VEELOGIC
100 nF to VCCLOG IC
7 pF to G NDDRIVE
7 pF to G NDDRIVE
100 nF to VCCIF
100 nF to VEEIF
see application circuit
see application circuit
100 nF to VEEIF
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ELECTRICAL SPECIFICATION (VVCCRF = 3.3 V ...5.9 V; VVCCIF = 3.3 V ...5.9 V; VVCC LOGIC = 3.3 V
...5.9 V VVCCDRIVE = 3 V; Ta = 25 oC unless otherwise specified)
LNA MIXER
Symb ol
IVCCRF
Zin
Zout
GC
IIP1
NF
fRF
fIF
P a ram et er
Supply Current
Differential Input
Impedance
Differential Output
Impedance
Voltage Conversion
Gain
Input Compression
Point (1dB)
Noise figure
Input Signal
Frequency (L1)
Output Signal
Frequency
Note
VVCCRF = 5 V
@ 1575 MHz AC Coupled at RF+
RF- inputs
@ 20 MHz AC Coupled at IF1+ IF1-
out pu t s
RL > 3K, PIN = -80 dBm
(Vin = 75 µVp on 300 )
(see application circuit)
Min.
20
35
-60
Typ .
300
1
70
3
M a x.
25
Unit
mA
pF
pF
dB
dBm
5
1575
dB
MHz
20 MHz
LO INPUT BUFFER
Symb ol
Zin
P a ram et er
Differential Input
Impedance
Input Signal Level
Note
@ 1555 MHz AC Coupled at LO+
LO - inputs
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Min.
-60
Typ .
300
1
-40
M a x.
-20
Unit
pF
dBm
LIMITING AMPLIFIER
Symb ol
IVCCIF
Zin
B
Sens
VI NMAX
P a ram et er
Supply Current
Differential Input
Impedance
Bandwidth 3dB
Limiter sensitivity
Maximum Input Signal
Note
VVCCIF = 5 V
@ 20 MHz AC Coupled at IF2+ IF2-
in put s
Input Signal @ 20 MHz AC Coupled
Input Signal @ 20 MHz AC Coupled
Min.
2.5
5
Typ .
15
100
M a x.
3.5
80
0.5
Unit
mA
K
MHz
µVp
Vp
CLOCK INPUT BUFFER
Symb ol
P a ram et er
IVCCLOGIC Supply Current
Zin Differential Input
Impedance
Input Signal Level
N Division Ratio
Note
VVCC LOGIC = 5 V
@ 80 MHz AC Coupled at 8O MHz+
80 MHz- inputs
@ 80 MHz AC Coupled at 8O MHz+
80 MHz- inputs
Min.
5
5
Typ .
8
2
5
M a x.
7
100
Unit
mA
K
pF
mVp
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ELECTRICAL CHARACTERISTICS (Continued)
OUTPUT SECTION
Symb ol
P a ram et er
IVCCDRIVE Supply Current
VOH High output voltage
VOL Low output volt age
tr Rise Time
tf Fall Time
Note
VVCCDRIVE = 3 V
Vp = VVCCDRIVE = 3 V
Vn = GNDDRIVE
CLOAD = 7 pF
CLOAD = 7 pF
STB5600
Min.
Vp-0.4
Vn
Typ .
8
6
2
M ax.
Vp
Vn +0. 4
Unit
mA
V
V
ns
ns
APPLICATION CIRCUIT
A typical application circuit is shown in figure 1. The RF input from the antenna downlead is fed via a
ceramic filter and matching circuit to the RF+,RF- pins. The external LNA in the antenna should have
between 10 and 35dB of amplifier gain, so the noise measured in a one MHz bandwidth should be
-114dBm for kTB in 1 MHz
+ 2dB LNA noise figure
+10/35 dB LNA gain (net)
Total -102/ 77dBm at connector.
Allowing 2dB for filter loss, -104/-79 is available at the matching circuit.
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Fig. 1 Typical Application Circuit
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