INF85116.pdf 데이터시트 (총 4 페이지) - 파일 다운로드 INF85116 데이타시트 다운로드

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INF85116
2048 х 8 -Bit CMOS EEPROM with I2С-bus interface
The INF85116N is an 16-Kbits (2048 x 8-bit) floating
gate Electrically Erasable Programmable Read Only
Memory (EEPROM). Power consumption is low due to
the full CMOS technology used. The programming
voltage is generated on-chip, using a voltage multi-
plier. As data bytes are received and transmitted via
the serial I2C-bus, a package using eight pins is suffi-
cient. Only one INF85116N device is required to sup-
port all eight blocks of 256 x 8-bit each.
FEATURES
Low power CMOS
-maximum active current 1.0 mA
-maximum standby current 10 µA (at 5.5 V), typical 4 µA
Non-volatile storage of 16-Kbits organized as eight blocks of 256x8-bits during 20 years
( at 55oC )
Single supply (Ucc=2,7 ÷ 5,5 V);
Automatically increased word's address
On-chip voltage multiplier
Serial input/output I2C-bus
1000000 ERASE/WRITE cycles per byte
Internal timer for writing (no external components)
Write operations: multi byte wDritaetamShoedeet4Uto.c3o2m bytes
DataShee
Write - protection input
Power-on-reset
Temperature range: -40oC ÷ +85oC
Simbol
n. c.
n. c
n. c
Uss
SDA
SCL
WP
Ucc
PIN DESCRIPTION
Pin Description
1 not connected
2 not connected
3 not connected
4 negative supply voltage
5 serial data input/output ( I2C-
6 bus)
7 serial clock input ( I2C-bus)
8 write - protection input
positive supply voltage
PIN CONFIGURATION
n. c. 1
8
n. c. 2
7
INF85116N
n. c. 3
6
Ucc
WP
SCL
Uss 4
5 SDA
Table 1. Quick reference data
Symbol
Parameter
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min max
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UDD
IOL
Tamb
SCL
6
5
SDA
8 VDD
VSS
INF85116
Supply voltage
LOW level output current
Operating ambient temperature
2.7
-
-40
BLOCK DIAGRAM
Input filter
Test mode
register
I2C-bus control logic
Address
comparator
Shift
register
5.5 V
6 mА
+85 °С
7 WP
Address
pointer
Sequenser
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Column decoder
Page register
Power-on-reset
EEPROM ARRAY
(8x256x8)
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4 VSS
Table 2. Limiting values
Symbol
UDD
Ui
Ii
Io
Tstg
Parameter
Supply voltage
Input voltage on any pin
/Zi/>500
Input current on any pin
Output current
Storage temperature
HV
generator
Row
dec
Divider
Oscillator
DataShee
min max Unit
-0.3 6.5
V
-0.8 6.5
V
- 1 mА
- 10 mА
-65 +150 °С
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INF85116
Table 3. Characteristics
Symbol
Parameter
Conditions
min
max
IDD(stb)
Standby supply current
UDD = 2.7V
UDD = 5.5V
-
6
10
ICCR Supply current READ
ICCW Supply current E / W
WP input (pin 7)
fSСL=400кHz,
UDD = 5.5V
fSСL=400кHz,
UDD = 5.5V
-
-
1
1
UIL LOW level input voltage
UIH HIGH level input voltage
SCL input (pin 6)
-0.8
0.9UDD
+0.1UDD
UDD+0.8
UIL LOW level input voltage
-0.8 +0.3UDD
UIH HIGH level input voltage
0.7UDD
6.5
ILI
Input leakage current
UI=UDD or USS
-
±1
fSCL Clock input frequency
tsp Pulse width of spikes sup-
pressed
0 400
0
100
by filter
СI Input capacitance
SDA input/output (pin 5)
UI= USS
-7
UIL
UIH
UOL1
UOL2
ILO
LOW level input voltage
HIGH level input voltage
LOW level output voltage IOL=3mА,
UDD = UDD (min)
IOL=6mА,
UDD = UDD (min)
Output leakage curreDntataSheUetO4HU=.UcoDDm
-0.8
0.7UDD
-
-
0.3UDD
6.5
0.4
0.6
1
tO(F)
Output fall time from UIHmin
to UILmax
with up to 3mА sink
current at UOL1
20+0.1 CB*
250
with up to 6mА sink
current at UOL2
tSP Pulse width of spikes sup-
pressed
20+0.1 CB
0
250
100
by filter
СI
tE/W
NE/W
tS
Input capacitance
E/W cycle time
E/W cycle per byte
Data retention time
UI=0V
ТТaammbb==(2-420оС-+85) оС,
Тamb = 55оС
-
-
100000
1000000
20
10
10
-
-
- The bus capacitance ranges from 10 to 400pF ( CB = total capacitance of one bus line in pF)
Unit
µА
µА
mА
mА
V
V
V
V
µА
kHz
ns
pF
V
V
V
µА DataShee
ns
ns
ns
pF
ms
years
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INF85116
Таble 4. I2C-bus characteristics
Symbol
Parameter
Condi-
Standard
Fast mode Unit
tions
mode
min max min max
fSCL Clock frequency
tBUF Time the bus must be free before
0 100 0 400 kHz
- 4.7 - 1.3 - µs
tHD, STA
START condition hold time after which
first clock pulse is generated
-
4.0 - 0.6 - µs
tLOW LOW level clock period
- 4.7 - 1.3 - µs
tHIGH
HIGH level clock period
- 4.0 - 0.6 - µs
tSU, STA
Set-up time for START condition
repeated
4.7
-
0.6 - µs
start
tHD, DAT
Data hold time for CBUS compatible
masters
-
5 - - - µs
tHD, DAT
tSU, DAT
tR
tF
tSU, STO
Data hold time for I2C - bus devices
Data set-up time
SDA and SCL rise time
SDA and SCL fall time
Set-up time for STOP condition
note 1
-
-
-
-
0 - 0 - ns
250 - 100 - ns
- 1000 20+0. 300 ns
1 Cb(2)
- 300 20+0. 300 ns
1 Cb(2)
4.0 - 0.6 - µs
Notes:
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of
SCL must be internally provided by a transmitter.
2. Cb = total capacitance of one bus line in pF.
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