MX23L4100.pdf 데이터시트 (총 7 페이지) - 파일 다운로드 MX23L4100 데이타시트 다운로드

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FEATURES
• Bit organization
- 512K x 8 (byte mode)
- 256K x 16 (word mode)
• Fast access time
- Random access: 100ns
• Current
- Operating: 30mA
- Standby: 20uA
• Supply voltage
- 3.3V±10%
• Package
- 40 pin SOP (500 mil)
- 40 pin PDIP (600 mil)
MX23L4100
4M-BIT MASK ROM (8/16 BIT OUTPUT)
ORDER INFORMATION
Part No.
MX23L4100MC-10
MX23L4100MC-12
MX23L4100MC-15
MX23L4100PC-10
MX23L4100PC-12
MX23L4100PC-15
Access Time
100ns
120ns
150ns
100ns
120ns
150ns
Package
40 pin SOP
40 pin SOP
40 pin SOP
40 pin PDIP
40 pin PDIP
40 pin PDIP
PIN CONFIGURATION
40 SOP
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A8
39 A9
38 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE
30 VSS
29 D15/A-1
28 D7
27 D14
26 D6
25 D13
24 D5
23 D12
22 D4
21 VCC
40 PDIP
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A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A8
39 A9
38 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE
30 VSS
29 D15/A-1
28 D7
27 D14
26 D6
25 D13
24 D5
23 D12
22 D4
21 VCC
PIN DESCRIPTION
Symbol
A0~A17
D0~D14
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OE
Byte
VCC
VSS
NC
Pin Function
Address Inputs
Data Outputs
Chip Enable Input
Output Enable Input
Word/ Byte Mode Selection
Power Supply Pin
Ground Pin
No Connection
DataShee
MODE SELECTION
CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Power
H X X X High Z High Z - Stand-by
L HX
X High Z High Z -
Active
L L H Output D0~D7 D8~D15 Word Active
L L L Input D0~D7 High Z Byte Active
REV. 1.6, JUN. 19, 2003
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BLOCK DIAGRAM
A0/(A-1)
A17
CE
BYTE
OE
Address
Buffer
Memory
Array
Sense
Amplifier
Word/
Byte
MX23L4100
Output
Buffer
D0
D15/(D7)
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ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Voltage on any Pin Relative to VSS
VIN
Ambient Operating Temperature
Topr
Storage Temperature
Tstg
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Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -0.8V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transi-
tions, input may overshoot VCC to VCC+2.0V for peri-
ods of up to 20ns.
Ratings
-0.8V to VCC+2.0V (Note)
0°C to 70°C
-65°C to 125°C
DataShee
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current (CE toggle)
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ISTB1
ISTB2
CIN
COUT
MIN.
2.4V
-
2.2V
-0.3V
-
-
-
-
-
-
-
MAX.
-
0.4V
VCC+0.3V
0.8V
5uA
5uA
30mA
1mA
20uA
10pF
10pF
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Conditions
IOH = -0.4mA
IOL = 1.6mA
0V, VCC
0V, VCC
tRC=100ns, all output open
CE = VIH
CE > VCC - 0.2V
Ta = 25°C, f = 1MHZ
Ta = 25°C, f = 1MHZ
REV. 1.6, JUN. 19, 2003

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MX23L4100
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Time
Output Hold After Address
Output High Z Delay
Symbol
tRC
tAA
tACE
tOE
tOH
tHZ
23L4100-10
MIN. MAX.
100ns -
- 100ns
- 100ns
- 50ns
- 0ns
- 20ns
23L4100-12
MIN. MAX.
120ns -
- 120ns
- 120ns
- 60ns
- 0ns
- 20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaran-
teed by design over the full voltage and temperature op-
erating range - not tested.
23L4100-15
MIN. MAX.
150ns -
- 150ns
- 150ns
- 70ns
- 0ns
- 20ns
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AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
0.4V~2.4V
10ns
1.4V
1.4V
IOH (load)=-0.4mA
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DOUT
See Figure
IOL (load)=1.6mA
C<100pF
DataShee
TIMING DIAGRAM
ACCESS TIMING
ADD
CE
OE
DATA
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Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
ADD
tACE
ADD
tRC
ADD
tOE
tAA
VALID
tOH
VALID
3
tHZ
VALID
REV. 1.6, JUN. 19, 2003

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PACKAGE INFORMATION
MX23L4100
et4U.com
DataSheet4U.com
DataShee
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P/N:PM0344
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REV. 1.6, JUN. 19, 2003
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MX23L4100
et4U.com
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DataShee
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P/N:PM0344
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REV. 1.6, JUN. 19, 2003
5