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MX23L6411
64M-BIT (8M x 8 / 4M x 16) Mask ROM with Page Mode
FEATURES
• Bit organization
- 8M x 8 (byte mode)
- 4M x 16 (word mode)
• Fast access time
- Random access: 100ns (max.)
- Page access: 30ns (max.)
• Page Size
- 8 words per page
• Current
- Operating: 50mA
- Standby: 15uA (max.)
• Supply voltage
- 2.7V~3.6V
• Package
- 44 pin SOP (500 mil)
- 48 pin TSOP (12mm x 20mm)
PIN CONFIGURATION
44 SOP
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A20
43 A19
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 VSS
31 D15/A-1
30 D7
29 D14
28 D6
27 D13
26 D5
25 D12
24 D4
23 VCC
ORDER INFORMATION
Part No.
Access Page Access Package
Time
Time
MX23L6411MC-12 120ns
50ns
44 pin SOP
MX23L6411TC-12 120ns
50ns
48 pin TSOP
MX23L6411RC-12 120ns
50ns
48 pin TSOP
(Reverse type)
MX23L6411MC-10 100ns
30ns
44 pin SOP
MX23L6411TC-10 100ns
30ns
48 pin TSOP
MX23L6411RC-10 100ns
30ns
48 pin TSOP
(Reverse type)
PIN DESCRIPTION
Symbol
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A0~A21
D0~D14
D15/A-1
CE
OE
Byte
VCC
VSS
NC
Pin Function
Address Inputs
Data Outputs
D15 (Word Mode) / LSB Address (Byte
Mode)
Chip Enable Input
Output Enable Input
Word / Byte Mode Selection
Power Supply Pin
Ground Pin
No Connection
DataShee
MODE SELECTION
CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Power
H X X X High Z High Z - Stand-by
L H X X High Z High Z - Active
L L H Output D0~D7 D8~D15 Word Active
L L L Input D0~D7 High Z Byte Active
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REV. 3.0, NOV. 22, 2002
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48 TSOP (NORMAL TYPE)
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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48 TSOP (REVERSE TYPE)
VSS
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
VCC
NC
D11
D3
D10
D2
D9
D1
D8
D0
OE
VSS
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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MX23L6411
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MX23L6411
48 VSS
47 VSS
46 D15/A-1
45 D7
44 D14
43 D6
42 D13
41 D5
40 D12
39 D4
38 VCC
37 VCC
36 NC
35 D11
34 D3
33 D10
32 D2
31 D9
30 D1
29 D8
28 D0
27 OE
26 VSS
25 VSS
DataShee
MX23L6411
1 BYTE
2 A16
3 A15
4 A14
5 A13
6 A12
7 A11
8 A10
9 A9
10 A8
11 A19
12 A21
13 A20
14 A18
15 A17
16 A7
17 A6
18 A5
19 A4
20 A3
21 A2
22 A1
23 A0
24 CE
REV. 3.0, NOV. 22, 2002
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MX23L6411
BLOCK DIAGRAM
A0/(A-1)
A2
A3
A21
CE
BYTE
OE
Address
Buffer
Memory
Array
Page
Buffer
Page
Decoder
Word/
Byte
Output
Buffer
D0
D15/(D7)
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ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage Relative to VSS
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
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Symbol
VCC
VIN
Topr
Tstg
Ratings
-0.3V to 4.3V
-0.5V to VCC + 2V
0°C to 70°C
-65°C to 125°C
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MX23L6411
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 2.7V~3.6V)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ISTB1
ISTB2
CIN
COUT
MIN.
2.4V
-
2.2V
-0.3V
-
-
-
-
-
-
-
MAX.
-
0.4V
VCC+0.3V
0.8V
5uA
5uA
50mA
1mA
15uA
10pF
10pF
Conditions
IOH = -0.4mA
IOL = 1.6mA
0V, VCC
0V, VCC
f=5MHz, all output open
CE = VIH
CE>VCC-0.2V
Ta = 25°C, f = 1MHZ
Ta = 25°C, f = 1MHZ
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AC CHARACTERISTICS (Ta = 0°C ~ 70°CD,aVtaCSChe=et24.U7.Vco~m3.6V)
Item
Symbol
Read Cycle Time
Address Access Time
Chip Enable Access Time
Page Mode Access Time
Output Enable Time
Output Hold After Address
Output High Z Delay
tRC
tAA
tACE
tPA
tOE
tOH
tHZ
23L6411-10
MIN.
MAX.
100ns
-
- 100ns
- 100ns
- 30ns
- 30ns
0ns -
- 20ns
Note:Output high-impedance delay (tHZ) is measured from
OE or CE going high, and this parameter guaranteed by
design over the full voltage and temperature operating
range - not tested.
23L6411-12
MIN.
MAX.
120ns
-
- 120ns
- 120ns
- 50ns
- 50ns
0ns -
- 20ns
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REV. 3.0, NOV. 22, 2002
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AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
0.4V~ 2.4V
10ns
1.4V
1.4V
See Figure
MX23L6411
IOH (load)=-0.4mA
DOUT
IOL (load)=1.6mA
C<100pF
TIMING DIAGRAM
RANDOM READ
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ADD
CE#
OE#
DATA
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
ADD
tACE
tOE
ADD
tRC
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ADD
tAA
VALID
tOH
VALID
tHZ
VALID
DataShee
PAGE READ
A3-A21
VALID ADD
(A-1),A0,A1,A2
DATA
1'st ADD
2'nd ADD
3'rd ADD
tAA tPA
VALID
VALID
VALID
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Note: CE, OE are enable.
Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.
5
REV. 3.0, NOV. 22, 2002