MX23L8111.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 MX23L8111 데이타시트 다운로드

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FEATURES
• Bit organization
- 1M x 8 (byte mode)
- 512K x 16 (word mode)
• Fast access time
- Random access: 100ns (max.)
- Page access: 30ns (max.)
• Current
- Operating: 20mA
- Standby: 20uA
• Supply voltage
- 100ns @3.0V ~ 3.6V
- 120ns @2.7V ~ 3.6V
• Package
- 44 pin SOP (500mil)
- 42 pin PDIP (600mil)
- 48 pin TSOP (type 1)
- 44 pin TSOP (type 2)
PIN CONFIGURATION
44 SOP/44TSOP
42PDIP
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 NC
43 NC
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 VSS
31 D15/A-1
30 D7
29 D14
28 D6
27 D13
26 D5
25 D12
24 D4
23 VCC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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MX23L8111
8M-BIT MASK ROM(8/16 BIT OUTPUT)
ORDER INFORMATION
Part No.
Access
Page Package
Time Access Time
MX23L8111MC-10 100ns
30ns 44 pin SOP
MX23L8111MC-12 120ns
60ns 44 pin SOP
MX23L8111PC-10 100ns
30ns 42 pin PDIP
MX23L8111PC-12 120ns
60ns 42 pin PDIP
MX23L8111TC-10 100ns
50ns 48 pin TSOP
MX23L8111TC-12 120ns
60ns 48 pin TSOP
MX23L8111RC-10 100ns
50ns 48 pin RTSOP
MX23L8111RC-12 120ns
60ns 48 pin RTSOP
MX23L8111YC-10 100ns
50ns 44 pin TSOP
MX23L8111YC-12 120ns
60ns 44 pin TSOP
Note: 48-TSOP and 48-RTSOP support word mode only, not
for byte mode.
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48 TSOP (for word mode only)
42 NC
41 A8
40 A9
39 A10
38 A11
37 A12
36 A13
35 A14
34 A15
33 A16
32 BYTE
31 VSS
30 D15/A-1
29 D7
28 D14
27 D6
26 D13
25 D5
24 D12
23 D4
22 VCC
NC
A16
A15
A14
A13
A12
A11
A10
A9
A8
NC
VSS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX23L8111
(Normal Type)
48 Reverse TSOP (for word mode only)
VSS
VSS
D15
D7
D14
D6
D13
D5
D12
D4
VCC
VCC
NC
D11
D3
D10
D2
D9
D1
D8
D0
OE
VSS
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX23L8111
(Reverse Type)
48 VSS
47 VSS
46 D15
45 D7
44 D14
43 D6
42 D13
41 D5
40 D12
39 D4
38 VCC
37 VCC
36 NC
35 D11
34 D3
33 D10
32 D2
31 D9
30 D1
29 D8
28 D0
27 OE
26 VSS
25 VSS
1 NC
2 A16
3 A15
4 A14
5 A13
6 A12
7 A11
8 A10
9 A9
10 A8
11 NC
12 VSS
13 NC
14 A18
15 A17
16 A7
17 A6
18 A5
19 A4
20 A3
21 A2
22 A1
23 A0
24 CE
DataShee
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MX23L8111
PIN DESCRIPTION
Symbol
A0~A18
D0~D14
D15/A-1
CE
OE
Byte
VCC
VSS
NC
Pin Function
Address Inputs
Data Outputs
D15(Word Mode)/LSB Address (Byte
Mode)
Chip Enable Input
Output Enable Input
Word/Byte Mode Selection
Power Supply Pin
Ground Pin
No Connection
MODE SELECTION
CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Power
HX X
X High Z High Z - Stand-by
LH X
X High Z High Z -
Active
L L H Output D0~D7 D8~D15 Word Active
L L L Input D0~D7 High Z Byte Active
BLOCK DIAGRAM
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A0/(A-1)
A2
A3
A18
CE
BYTE
OE
Address
Buffer
Memory
Array
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Page
Buffer
Page
Decoder
Double
Word
Output
Buffer
D0
D15/(D7)
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ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
Symbol
VIN
Topr
Tstg
Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transi-
tions, input may overshoot VCC to VCC+2.0V for peri-
ods of up to 20ns.
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2
Ratings
-1.3V to VCC+2.0V (Note)
0°C to 70°C
-65°C to 125°C
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MX23L8111
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ISTB1
ISTB2
CIN
COUT
MIN.
24V
-
2.2V
-0.3V
-
-
-
-
-
-
-
MAX.
-
0.4V
VCC+0.3V
0.8V
5uA
5uA
20mA
1mA
20uA
10pF
10pF
Conditions
IOH = -0.4mA
IOL = 1.6mA
0V, VCC
0V, VCC
f=10MHz, all output open
CE=VIH
CE> VCC - 0.2V
Ta = 25°C, f = 1MHZ
Ta = 25°C, f = 1MHZ
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
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Item
Read Cycle Time
Address Access Time
Chip Enable Access Time
Page Mode Access Time
Output Enable Time
Output Hold After Address
Output High Z Delay
Symbol
tRC
tAA
tACE
tPA
tOE
tOH
tHZ
23L8111-10
MIN. MAX.
1D0a0tnasShee- t4U.com
- 100ns
- 100ns
- 30ns*
- 30ns*
0ns -
- 20ns
23L8111-12
MIN. MAX.
120ns -
- 120ns
- 120ns
- 60ns
- 60ns
0ns -
- 20ns
DataShee
Note: Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by
design over the full voltage and temperature operating range - not tested.
* For 100ns speed grade, tPA and tOE spec are 30ns for PDIP and SOP package types, but 50ns for TSOP package
type.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
0.4V~2.4V
10ns
1.4V
1.4V
See Figure
IOH (load)=-0.4mA
DOUT
IOL (load)=1.6mA
C<100pF
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Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
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TIMING DIAGRAM
RANDOM READ
ADD
CE
OE
DATA
MX23L8111
ADD
tACE
ADD
tRC
ADD
tOE
tAA
VALID
tOH
VALID
tHZ
VALID
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A3-A18
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VALID ADD
(A-1),A0,A1,A2
DATA
1'st ADD
2'nd ADD 3'rd ADD
tAA tPA
VALID
VALID
VALID
Note: CE, OE are enable.
Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.
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PACKAGE INFORMATION
MX23L8111
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