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FLASH MEMORY
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
MT28F002B5
MT28F200B5
5V Only, Dual Supply (Smart 5)
FEATURES
• Five erase blocks:
40-Pin TSOP Type I 48-Pin TSOP Type I
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Two main memory blocks
• Smart 5 technology (B5):
5V ±10% VCC
5V ±10% VPP application/production
programming
12V ±5% VPP compatibility production
44-Pin SOP
programming
• Address access times: 60ns, 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
DataShee
• Byte- or word-wide READ and WRITE
(MT28F200B5, 128K x 16/256K x 8)
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• Byte-wide READ and WRITE only
(MT28F002B5, 256K x 8)
• TSOP and SOP packaging options
GENERAL DESCRIPTION
The MT28F002B5 (x8) and MT28F200B5 (x16/x8)
are nonvolatile, electrically block-erasable (flash), pro-
OPTIONS
MARKING
grammable, read-only memories containing 2,097,152
• Timing
bits organized as 262,144 bytes (8 bits) or 131,072
60ns access
-6 words (16 bits). Writing or erasing the device is done
80ns access
-8 with a 5V VPP voltage, while all operations are per-
80ns access
-8 ET
formed with a 5V VCC. Due to process technology
• Configurations
256K x 8
128K x 16/256K x 8
• Boot Block Starting Word Address
Top (1FFFFH)
Bottom (00000H)
MT28F002B5
MT28F200B5
T
B
advances, 5V VPP is optimal for application and produc-
tion programming. For backward compatibility with
SmartVoltage technology, 12V VPP is supported for a
maximum of 100 cycles and may be connected for up
to 100 cumulative hours. These devices are fabricated
with Micron’s advanced CMOS floating-gate process.
The MT28F002B5 and MT28F200B5 are organized
• Operating Temperature Range
into five separately erasable blocks. To ensure that
Commercial (0°C to +70°C)
None
critical firmware is protected from accidental erasure or
Extended (-40°C to +85°C)
ET overwrite, the devices feature a hardware-protected
• Packages
Plastic 44-pin SOP (600 mil)
Plastic 48-pin TSOP Type 1
(12mm x 20mm)
Plastic 40-pin TSOP
(10mm x 20mm)
boot block. Writing or erasing the boot block requires
SG either applying a super-voltage to the RP# pin or driv-
WG ing WP# HIGH in addition to executing the normal
write or erase sequences. This block may be used to store
VG code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
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Part Number Example:
MT28F200B5SG-8 T
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html) for the latest data sheet.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN ASSIGNMENT (Top View)
48-Pin TSOP Type I
44-Pin SOP
et4U.com
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE#
46 VSS
45 DQ15/(A - 1)
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
ORDER NUMBER AND PART MARKING
MT28F200B5WG-6 B
MT28F200B5WG-6 T
MT28F200B5WG-8 B
MT28F200B5WG-8 T
MT28F200B5WG-8 BET
MT28F200B5WG-8 TET
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VPP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RP#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 DQ15/(A - 1)
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
ORDER NUMBER AND PART MARKING
MT28F200B5SG-6 B
MT28F200B5SG-6 T
MT28F200B5SG-8 B
MT28F200B5SG-8 T
MT28F200B5SG-8 BET
MT28F200B5SG-8 TET
40-Pin TSOP Type I
DataShee
DataSheet4U.com
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A17
39 VSS
38 NC
37 NC
36 A10
35 DQ7
34 DQ6
33 DQ5
32 DQ4
31 VCC
30 VCC
29 NC
28 DQ3
27 DQ2
26 DQ1
25 DQ0
24 OE#
23 VSS
22 CE#
21 A0
ORDER NUMBER AND PART MARKING
MT28F002B5VG-6 B
MT28F002B5VG-6 T
MT28F002B5VG-8 B
MT28F002B5VG-8 T
MT28F002B5VG-8 BET
MT28F002B5VG-8 TET
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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BYTE#1
A0-A16/(A17)
WP#
CE#
OE#
WE#
RP#
VCC
VPP
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2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
I/O
Control
Logic
A9
Addr.
Buffer/
Latch
18 (19)
Power
(Current)
Control
Addr.
Counter
Command
Execution
Logic
State
Machine
VPP
Switch/
Pump
Status
Register
Input
8 Buffer
9
9
(10)
16KB Boot Block
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
7
Input
Buffer
Input Data
Latch/Mux
16
Input
Buffer
(A - 1)
Y-
Decoder
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
Identification
Register
DQ15
7
8
DataSheet4U.com
8
Output
Buffer
Output
Buffer
Output
Buffer
7
8
DQ15/(A - 1)1
DQ8-DQ141
DQ0-DQ7
DataShee
NOTE 1. Does not apply to MT28F002B5.
DataSheet4U.com
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
DataSheet4 U .com
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.

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2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
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44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL TYPE
DESCRIPTION
43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP =
VPPH1 (5V) or VPPH2 (12V)1 and RP# = VIH during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
12 22 26 CE# Input Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at VHH (12V), and must be held at VIH during all
other modes of operation.
14 24 28 OE# Input Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active through
DataSheeDt4QU8.-cDoQm15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/(A - 1) becomes the
least significant address input.
11, 10, 9, 8,
7, 6, 5, 4,
42, 41, 40,
39, 38, 37,
36, 35, 34
21, 20, 19,
18, 17, 16,
15, 14, 8, 7,
36, 6, 5, 4, 3,
2, 1, 40
25, 24, 23,
22, 21, 20,
19, 18, 8, 7,
6, 5, 4, 3, 2,
1, 48
A0-A16/
(A17)
Input
Address Inputs: Select a unique, 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F200B5) to allow for a selection of an
8-bit byte from the 262,144 available.
31 – 45 DQ15 Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
(A - 1) Output of address input when BYTE# = LOW during READ or WRITE
operation.
15, 17, 19, 25-28, 32-35 29, 31, 33,
21, 24, 26,
35, 38, 40,
28, 30
42, 44
DQ0-DQ7 Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to input
commands to the CEL.
16, 18, 20, – 30, 32, 34, DQ8-DQ14 Input/ Data I/Os: Data output pins during any READ operation or
22, 25, 27,
36, 39, 41,
Output data input pins during a WRITE when BYTE# = HIGH. These
29 43
pins are High-Z when BYTE# is LOW.
1 11 13 VPP Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, VPP must be at VPPH1
(5V) or VPPH2 (12V)1. VPP = “Don’t Care” during all other
operations.
23 30, 31 37 VCC Supply Power Supply: +5V ±10%.
13, 32
23, 39
27, 46
VSS Supply Ground.
3
13, 29, 37, 38 9, 10, 15-17
NC
– No Connect: These pins may be driven or left unconnected.
DataShee
NOTE: 1. For SmartVoltage-compatible production programming, 12V VPP is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours.
DataSheet4U.com
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F200B5)1
FUNCTION
RP# CE# OE# WE# WP# BYTE# A0 A9 VPP DQ0-DQ7 DQ8-DQ14 DQ15/A - 1
Standby
H H X X X X X X X High-Z High-Z High-Z
RESET
L X X X X X X X X High-Z High-Z High-Z
READ
READ (word mode)
H L L H X H X X X Data-Out Data-Out Data-Out
READ (byte mode)
H L L H X L X X X Data-Out High-Z A - 1
Output Disable
H L H H X X X X X High-Z High-Z High-Z
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP
ERASE CONFIRM3
H L H L X X XX X
20H
H L H L X X X X VPPH D0H
X
X
X
X
WRITE SETUP
WRITE (word mode)4
WRITE (byte mode)4
READ ARRAY5
WRITE/ERASE (BOOT BLOCK)2, 7
H L H L X X X X X 10H/40H
X
X
H L H L X H X X VPPH Data-In Data-In Data-In
H L H L X L X X VPPH Data-In
X
A-1
H L H L X X XX X
FFH
X
X
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ERASE SETUP
ERASE CONFIRM3
ERASE CONFIRM3, 6
WRITE SETUP
WRITE (word mode)4
WRITE (word mode)4, 6
WRITE (byte mode)4
WRITE (byte mode)4, 6
READ ARRAY5
DEVICE IDENTIFICATION8, 9
H L H L X X XX X
20H
X
X
VHH L H L X X X X VPPH D0H
X
X DataShee
H L H L H X X X VPPH D0H
H L DaHtaSheLet4UX.comX X X X 10H/40H
X
X
X
X
VHH L H L X H X X VPPH Data-In Data-In Data-In
H L H L H H X X VPPH Data-In Data-In Data-In
VHH L H L X L X X VPPH Data-In
X
A-1
H L H L H L X X VPPH Data-In
X
A-1
H L H L X X XX X
FFH
X
X
Manufacturer Compatibility
(word mode)10
HL
L H X H L VID X
89H
00H
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)10
HL
HL
L H X L L VID X
L H X H H VID X
89H High-Z
74H 22H
X
Device (byte mode, top boot)
Device (word mode, bottom boot) 10
HL
HL
L H X L H VID X
L H X H H VID X
74H High-Z
75H 22H
X
Device (byte mode, bottom boot)
H L L H X L H VID X
75H High-Z
X
NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
2. VPPH = VPPH1 = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. VHH = 12V.
8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
9. A1-A8, A10-A16 = VIL.
10. Value reflects DQ8-DQ15.
DataSheet4U.com
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
DataSheet4 U .com