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4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL TYPE
DESCRIPTION
43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE
cycle. If WE# is LOW, the cycle is either a WRITE to the
command execution logic (CEL) or to the memory array.
2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP
= VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a
WRITE or ERASE. Does not affect WRITE or ERASE
operation on other blocks.
12 22 26 CE# Input Chip Enable: Activates the device when LOW. When
CE# is HIGH, the device is disabled and goes into
standby power mode.
44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the
array read mode and places the device in deep power-
down mode. All inputs, including CE#, are “Don’t
Care,” and all outputs are High-Z. RP# unlocks the boot
block and overrides the condition of WP# when at VHH
(12V), and must be held at VIH during all other modes
of operation.
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14
24
28 OE# Input Output Enable: Enables data output buffers when
LOW. When OE# is HIGH, the output buffers are
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33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7.
DQ15/(A-1) becomes the least significant address input.
11, 10, 9, 8, 21, 20, 19, 25, 24, 23,
7, 6, 5, 4, 18, 17, 16, 22, 21, 20,
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7,
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2,
36, 35, 34, 3 2, 1, 40, 13 1, 48, 17
A0–A17/
(A18)
Input
Address Inputs: Select a unique, 16-bit word or 8-bit
byte. The DQ15/(A-1) input becomes the lowest order
address when BYTE# = LOW (MT28F400B3) to allow for
a selection of an 8-bit byte from the 524,288 available.
31 – 45 DQ15/ Input/ Data I/O: MSB of data when BYTE# = HIGH. Address
(A-1) Output Input: LSB of address input when BYTE# = LOW during
READ or WRITE operation.
15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0–DQ7 Input/ Data I/Os: Data output pins during any READ operation
21, 24, 26,
35, 38, 40,
Output or data input pins during a WRITE. These pins are used
28, 30
42, 44
to inputcommands to the CEL.
16, 18, 20, – 30, 32, 34, DQ8–DQ14 Input/ Data I/Os: Data output pins during any READ operation
22, 25, 27,
36, 39, 41,
Output or data input pins during a WRITE when BYTE# = HIGH.
29 43
These pins are High-Z when BYTE# is LOW.
1 11 13 VPP Supply Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH1 (3.3V) or VPPH2 (5V). VPP = “Don’t Care”
during all other operations.
23 30, 31 37
VCC Supply Power Supply: +3.3V ±0.3V.
13, 32
23, 39
27, 46
VSS Supply Ground.
– 29, 37, 38 9, 10, 15, 16 NC – No Connect: These pins may be driven or left
unconnected.
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DataShee
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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