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FLASH MEMORY
4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
MT28F004B3
MT28F400B3
3V Only, Dual Supply (Smart 3)
FEATURES
• Seven erase blocks:
16KB/8K-word boot block (protected)
40-Pin TSOP Type I 48-Pin TSOP Type I
Two 8KB/4K-word parameter blocks
Four main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V VCC
3.3V ±0.3V VPP application programming
5V ±10% VPP application/production programming1
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 80ns
• 100,000 ERASE cycles
44-Pin SOP
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F400B3, 256K x 16/512K x 8)
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• Byte-wide READ and WRITE only
(MT28F004B3, 512K x 8)
• TSOP and SOP packaging options
DataShee
OPTIONS
• Timing
80ns access
• Configurations
512K x 8
256K x 16/512K x 8
• Boot Block Starting Word Address
Top (3FFFFh)
Bottom (00000h)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
• Packages
44-pin SOP (MT28F400B3)
48-pin TSOP Type I (MT28F400B3)
40-pin TSOP Type I (MT28F004B3)
MARKING
-8
MT28F004B3
MT28F400B3
T
B
None
ET
SG
WG
VG
NOTE:
1. This generation of devices does not support 12V VPP
compatibility production programming; however, 5V VPP
application production programming can be used with no
loss of performance.
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Part Number Example:
MT28F400B3SG-8 T
GENERAL DESCRIPTION
The MT28F004B3 (x8) and MT28F400B3 (x16/x8)
are nonvolatile, electrically block-erasable (flash), pro-
grammable memory devices containing 4,194,304 bits
organized as 262,144 words (16 bits) or 524,288 bytes (8
bits). Writing or erasing the device is done with either a
3.3V or 5V VPP voltage, while all operations are performed
with a 3.3V VCC. Due to process technology advances,
5V VPP is optimal for application and production pro-
gramming. These devices are fabricated with Micron’s
advanced 0.18µm CMOS floating-gate process.
The MT28F004B3 and MT28F400B3 are organized
into seven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv-
ing WP# HIGH in addition to executing the normal write
or erase sequences. This block may be used to store
code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
1
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
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PIN ASSIGNMENT (Top View)
48-PIN TSOP TYPE I
44-PIN SOP
1 48 A16
2 47 BYTE#
3 46 VSS
4 45 DQ15/(A-1)
5 44 DQ7
6 43 DQ14
7 42 DQ6
8 41 DQ13
9 40 DQ5
10 39 DQ12
11 38 DQ4
12 37 VCC
13 36 DQ11
14 35 DQ3
15 34 DQ10
16 33 DQ2
17 32 DQ9
18 31 DQ1
19 30 DQ8
20 29 DQ0
21 28 OE#
22 27 VSS
23 26 CE#
24 25 A0
ORDER NUMBER AND PART MARKING
MT28F400B3WG-8 B
MT28F400B3WG-8 T
MT28F400B3WG-8 BET
MT28F400B3WG-8 TET
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VPP
WP#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RP#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 DQ15/(A-1)
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
ORDER NUMBER AND PART MARKING
MT28F400B3SG-8 B
MT28F400B3SG-8 T
MT28F400B3SG-8 BET
MT28F400B3SG-8 TET
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A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
40-PIN TSOP TYPE I
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
A17
VSS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
DataSheet4U.com
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
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ORDER NUMBER AND PART MARKING
MT28F004B3VG-8 B
MT28F004B3VG-8 T
MT28F004B3VG-8 BET
MT28F004B3VG-8 TET
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

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BYTE#1
A0–A17/(A18)
WP#
CE#
OE#
WE#
RP#
VCC
VPP
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4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
I/O
Control
Logic
A9
Addr.
Buffer/
Latch
18 (19)
Power
(Current)
Control
Addr.
Counter
Command
Execution
Logic
State
Machine
VPP
Switch/
Pump
Status
Register
Input
8 Buffer
9
9
(10)
16KB Boot Block
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
7
Input
Buffer
Input Data
Latch/Mux
16
Input
Buffer
A-1
Y-
Decoder
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
Identification
Register
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DQ15
7
8
8
Output
Buffer
Output
Buffer
Output
Buffer
7
8
DQ15/(A - 1)1
DQ8–DQ141
DQ0–DQ7
DataShee
NOTE: 1. Does not apply to MT28F004B3.
DataSheet4U.com
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
DataSheet4 U .com
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

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4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL TYPE
DESCRIPTION
43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE
cycle. If WE# is LOW, the cycle is either a WRITE to the
command execution logic (CEL) or to the memory array.
2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP
= VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a
WRITE or ERASE. Does not affect WRITE or ERASE
operation on other blocks.
12 22 26 CE# Input Chip Enable: Activates the device when LOW. When
CE# is HIGH, the device is disabled and goes into
standby power mode.
44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the
array read mode and places the device in deep power-
down mode. All inputs, including CE#, are “Don’t
Care,” and all outputs are High-Z. RP# unlocks the boot
block and overrides the condition of WP# when at VHH
(12V), and must be held at VIH during all other modes
of operation.
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14
24
28 OE# Input Output Enable: Enables data output buffers when
LOW. When OE# is HIGH, the output buffers are
DataSheedt4isUa.bcloemd.
33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7.
DQ15/(A-1) becomes the least significant address input.
11, 10, 9, 8, 21, 20, 19, 25, 24, 23,
7, 6, 5, 4, 18, 17, 16, 22, 21, 20,
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7,
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2,
36, 35, 34, 3 2, 1, 40, 13 1, 48, 17
A0–A17/
(A18)
Input
Address Inputs: Select a unique, 16-bit word or 8-bit
byte. The DQ15/(A-1) input becomes the lowest order
address when BYTE# = LOW (MT28F400B3) to allow for
a selection of an 8-bit byte from the 524,288 available.
31 – 45 DQ15/ Input/ Data I/O: MSB of data when BYTE# = HIGH. Address
(A-1) Output Input: LSB of address input when BYTE# = LOW during
READ or WRITE operation.
15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0–DQ7 Input/ Data I/Os: Data output pins during any READ operation
21, 24, 26,
35, 38, 40,
Output or data input pins during a WRITE. These pins are used
28, 30
42, 44
to inputcommands to the CEL.
16, 18, 20, – 30, 32, 34, DQ8–DQ14 Input/ Data I/Os: Data output pins during any READ operation
22, 25, 27,
36, 39, 41,
Output or data input pins during a WRITE when BYTE# = HIGH.
29 43
These pins are High-Z when BYTE# is LOW.
1 11 13 VPP Supply Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH1 (3.3V) or VPPH2 (5V). VPP = “Don’t Care”
during all other operations.
23 30, 31 37
VCC Supply Power Supply: +3.3V ±0.3V.
13, 32
23, 39
27, 46
VSS Supply Ground.
– 29, 37, 38 9, 10, 15, 16 NC – No Connect: These pins may be driven or left
unconnected.
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DataShee
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F400B3)1
FUNCTION
RP# CE# OE# WE# WP# BYTE# A0 A9 VPP DQ0–DQ7 DQ8–DQ14 DQ15/A-1
Standby
H H X X X X X X X High-Z High-Z High-Z
RESET
L X X X X X X X X High-Z High-Z High-Z
READ
READ (word mode)
H L L H X H X X X Data-Out Data-Out Data-Out
READ (byte mode)
H L L H X L X X X Data-Out High-Z A-1
Output Disable
HL
WRITE/ERASE (EXCEPT BOOT BLOCK)2
H H X X X X X High-Z High-Z High-Z
ERASE SETUP
ERASE CONFIRM3
H L H L X X X X X 20h
H L H L X X X X VPPH D0h
X
X
X
X
WRITE SETUP
H L H L X X X X X 10h/40h X
X
WRITE (word mode)4
H L H L X H X X VPPH Data-In Data-In Data-In
WRITE (byte mode)4
H L H L X L X X VPPH Data-In
X
A-1
READ ARRAY5
H L H L X X XX X
FFh
X
X
WRITE/ERASE (BOOT BLOCK)2, 7
ERASE SETUP
H L H L X X X X X 20h
X
X
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ERASE CONFIRM3
ERASE CONFIRM3, 6
WRITE SETUP
VHH L H L X X X X VPPH D0h
H L H L H X X X VPPH D0h
H L DaHtaSheLet4UX.comX X X X 10h/40h
X
X
X
X DataShee
X
X
WRITE (word mode)4
VHH L H L X H X X VPPH Data-In Data-In Data-In
WRITE (word mode)4, 6
H L H L H H X X VPPH Data-In Data-In Data-In
WRITE (byte mode)4
VHH L H L X L X X VPPH Data-In
X
A-1
WRITE (byte mode)4, 6
H L H L H L X X VPPH Data-In
X
A-1
READ ARRAY5
H L H L X X XX X
FFh
X
X
DEVICE IDENTIFICATION8, 9
Manufacturer Compatibility
(word mode)10
H L L H X H L VID X
89h
00h
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)10
HL
HL
L H X L L VID X
L H X H H VID X
89h High-Z
70h 44h
X
Device (byte mode, top boot)
H
Device (word mode, bottom boot) 10 H
L
L
L H X L H VID X
L H X H H VID X
70h High-Z
71h 44h
X
Device (byte mode, bottom boot) H L L H X L H VID X
71h High-Z
X
NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
2. VPPH = VPPH1 (3.3V) or VPPH2 (5V).
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. VHH = 12V.
8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
9. A1–A8, A10–A17 = VIL.
10. Value reflects DQ8–DQ15.
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4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
DataSheet4 U .com