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FLASH MEMORY
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
MT28F008B3
MT28F800B3
3V Only, Dual Supply (Smart 3)
FEATURES
• Eleven erase blocks:
16KB/8K-word boot block (protected)
40-Pin TSOP Type I 48-Pin TSOP Type I
Two 8KB/4K-word parameter blocks
Eight main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V VCC
3.3V ±0.3V VPP application programming
5V ±10% VPP application/production programming1
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 90ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
44-Pin SOP
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP, SOP and FBGA packaging options
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• Byte- or word-wide READ and WRITE
(MT28F800B3):
1 Meg x 8/512K x 16
DataShee
OPTIONS
• Timing
90ns access
• Configurations
1 Meg x 8
512K x 16/1 Meg x 8
• Boot Block Starting Word Address
Top (7FFFFh)
Bottom (00000h)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
• Packages
40-pin TSOP Type I (MT28F008B3)
48-pin TSOP Type I (MT28F800B3)
44-pin SOP (MT28F800B3)
MARKING
-9
MT28F008B3
MT28F800B3
T
B
None
ET
VG
WG
SG
NOTE:
1. This generation of devices does not support 12V VPP
production programming; however, 5V VPP application
production programming can be used with no loss of
performance.
Part Number Example:
MT28F800B3WG-9 BET
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GENERAL DESCRIPTION
The MT28F008B3 (x8) and MT28F800B3 (x16/x8) are
low-voltage, nonvolatile, electrically block-erasable (flash),
programmable memory devices containing 8,388,608 bits
organized as 524,288 words (16 bits) or 1,048,576 bytes (8
bits). Writing and erasing the device is done with a VPP
voltage of either 3.3V or 5V, while all operations are
performed with a 3.3V VCC. Due to process technology
advances, 5V VPP is optimal for application and production
programming. These devices are fabricated with Micron’s
advanced 0.18µm CMOS floating-gate process.
The MT28F008B3 and MT28F800B3 are organized
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code imple-
mented in low-level system recovery. The remaining
blocks vary in density and are written and erased with
no additional security measures.
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
1
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN ASSIGNMENT (Top View)
48-Pin TSOP Type I
44-Pin SOP
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE#
46 VSS
45 DQ15/(A - 1)
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
ORDER NUMBER AND PART MARKING
MT28F800B3WG-9 B
MT28F800B3WG-9 T
MT28F800B3WG-9 BET
MT28F800B3WG-9 TET
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VPP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RP#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 DQ15/(A - 1)
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
ORDER NUMBER AND PART MARKING
MT28F800B3SG-9 B
MT28F800B3SG-9 T
MT28F800B3SG-9 BET
MT28F800B3SG-9 TET
DataShee
DataSheet4U.com
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
DataSheet4 U .com
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
40-Pin TSOP Type I
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F008B3VG-9 B
MT28F008B3VG-9 T
MT28F008B3VG-9 BET
MT28F008B3VG-9 TET
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

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BYTE# 2
A0–A18/(A19)
WP# 1
CE#
OE#
WE#
RP#
VCC
VPP
FUNCTIONAL BLOCK DIAGRAM
I/O
Control
Logic
A9
Addr.
Buffer/
Latch
19 (20)
Power
(Current)
Control
Addr.
Counter
Command
Execution
Logic
State
Machine
VPP
Switch/
Pump
Status
Register
Input
8 Buffer
10
9
(10)
Y-
Decoder
Identification
Register
16KB Boot Block
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
7
Input
Buffer
Input Data
Latch/Mux
16
Input
Buffer
A-1
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
DQ15
7
8
8
Output
Buffer
Output
Buffer
Output
Buffer
7
8
DQ15/(A - 1) 2
DQ8–DQ14 2
DQ0–DQ7
NOTE: 1. Does not apply to MT28F800B3SG.
2. Does not apply to MT28F008B3.

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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL TYPE
DESCRIPTION
43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
– 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP =
VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
12 22 26 CE# Input Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at VHH (12V), and must be held at VIH during all
other modes of operation.
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14
24
28
OE# Input Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
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33 – 47 BYTE# DaItnapSuhteeBt4yUte.cEonmable: If BYTE# = HIGH, the upper byte is active through
DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all
data is accessed through DQ0–DQ7. DQ15/(A - 1) becomes the
least significant address input.
11, 10, 9, 8, 21, 20, 19, 18, 25, 24, 23,
7, 6, 5, 4, 42, 17, 16, 15, 14, 22, 21, 20,
41, 40, 39, 8, 7, 36, 6, 5, 19, 18, 8, 7,
38, 37, 36, 4, 3, 2, 1, 40, 6, 5, 4, 3, 2,
35, 34, 3, 2 13, 37 1, 48, 17, 16
A0–A18/
(A19)
Input
Address Inputs: Select a unique 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F800B3) to allow for a selection of an 8-
bit byte from the 1,048,576 available.
31 – 45 DQ15/ Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
(A - 1) Output of address input when BYTE# = LOW during READ or WRITE
operation.
15, 17, 19,
21, 24, 26,
28, 30
25, 26, 27,
28, 32, 33,
34, 35
29, 31, 33,
35, 38, 40,
42, 44
DQ0–
DQ7
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to input
commands to the CEL.
16, 18, 20, – 30, 32, 34, DQ8– Input/ Data I/Os: Data output pins during any READ operation or
22, 25, 27,
36, 39, 41, DQ14 Output data input pins during a WRITE when BYTE# = HIGH. These
29 43
pins are High-Z when BYTE# is LOW.
1 11 13 VPP Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, VPP must be at VPPH1
(3.3V) or VPPH2 (5V). VPP = “Don’t Care” during all other
operations.
23 30, 31 37
VCC Supply Power Supply: +3.3V ±0.3V.
13, 32
23, 39
27, 46
VSS Supply Ground.
29, 38
9, 10, 15
NC
– No Connect: These pins may be driven or left unconnected.
DataSheet4U.com
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
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4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F800B3)1
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FUNCTION
RP# CE# OE# WE# WP# BYTE# A0 A9 VPP DQ0–DQ7 DQ8–DQ14 DQ15/A - 1
Standby
H H X X X X X X X High-Z High-Z High-Z
RESET
L X X X X X X X X High-Z High-Z High-Z
READ
READ (word mode)
H L L H X H X X X Data-Out Data-Out Data-Out
READ (byte mode)
H L L H X L X X X Data-Out High-Z A-1
Output Disable
HL
WRITE/ERASE (EXCEPT BOOT BLOCK)2
H H X X X X X High-Z High-Z High-Z
ERASE SETUP
ERASE CONFIRM3
H L H L X X X X X 20h
H L H L X X X X VPPH D0h
X
X
X
X
WRITE SETUP
H L H L X X X X X 10h/40h X
X
WRITE (word mode)4
H L H L X H X X VPPH Data-In Data-In Data-In
WRITE (byte mode)4
H L H L X L X X VPPH Data-In
X
A-1
READ ARRAY5
H L H L X X XX X
FFh
X
X
WRITE/ERASE (BOOT BLOCK)2, 7
ERASE SETUP
H L H L X X X X X 20h
X
X
ERASE CONFIRM3
ERASE CONFIRM3, 6
WRITE SETUP
VHH L H L X X X X VPPH D0h
H L H L H X X X VPPH D0h
H L DaHtaSheLet4UX.comX X X X 10h/40h
X
X
X
X DataShee
X
X
WRITE (word mode)4
VHH L H L X H X X VPPH Data-In Data-In Data-In
WRITE (word mode)4, 6
H L H L H H X X VPPH Data-In Data-In Data-In
WRITE (byte mode)4
VHH L H L X L X X VPPH Data-In
X
A-1
WRITE (byte mode)4, 6
H L H L H L X X VPPH Data-In
X
A-1
READ ARRAY5
H L H L X X XX X
FFh
X
X
DEVICE IDENTIFICATION8, 9
Manufacturer Compatibility
(word mode)10
H L L H X H L VID X
89h
00h
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)10
HL
HL
L H X L L VID X
L H X H H VID X
89h High-Z
9Ch 88h
X
Device (byte mode, top boot)
Device (word mode, bottom boot)10
H
H
L
L
L H X L H VID X
L H X H H VID X
9Ch High-Z
9Dh 88h
X
Device (byte mode, bottom boot) H L L H X L H VID X
9Dh High-Z
X
NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. VHH = 12V.
8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
9. A1–A8, A10–A18 = VIL.
10. Value reflects DQ8–DQ15.
DataSheet4U.com
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
DataSheet4 U .com