MB91F109.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 MB91F109 데이타시트 다운로드

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FUJITSU SEMICONDUCTOR
DATA SHEET
32-bit RISC Microcontroller
CMOS
FR Family MB91F109
DS07-16304-1E
MB91F109
s DESCRIPTION
The MB91F109 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)
core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU
processing for embedded controller applications. To carry out hi-speed performance of CPU instructions, in-
struction/data Flash memory of 254 Kbytes and RAM of 2 Kbytes + 2 Kbytes are embedded in the MB91F109.
The MB91F109 is optimized for applications requiring high-performance CPU processing such as navigation
systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.
s FEATURES
FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency: Internal 25 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
• General purpose registers: 32 bits × 16
• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions
(Continued)
s PACKAGES
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-100P-M05)
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(FPT-100P-M06)

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MB91F109
(Continued)
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (push PC and PS): 6 cycles, 16 priority levels
External bus interface
• Without Clock doubler: Maximum internal bus 25 MHz, maximum external bus 25 MHz operation
• 25-bit address bus (32 Mbytes memory space)
• 8/16-bit data bus
• Basic external bus cycle: 2 clock cycles
• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
• Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured us input/output ports
• Little endian mode supported (Select 1 area from area 1 to 5)
DRAM interface
• 2 banks independent control (area 4 and 5)
• Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
• Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
• Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
• DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
DMA controller (DMAC)
• 8 channels
• Transfer incident/external pins/internal resource interrupt requests
• Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
• Transfer data length: 8 bits/16 bits/32 bits selective
• NMI/interrupt request enables temporary stop operation
UART
• 3 independent channels
• Full-duplex double buffer
• Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
• Asynchronous (start-stop system), CLK-synchronized communication selective
• Multi-processor mode
• Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
• Use external clock can be used as a transfer clock
• Error detection: Parity, frame, overrun
10-bit A/D converter (successive approximation conversion type)
• 10-bit resolution, 4 channels
• Successive approximation type: Conversion time of 5.6 µs at 25 MHz
• Internal sample and hold circuit
• Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective
• Start: Software/external trigger/internal timer selective
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MB91F109
(Continued)
16-bit reload timer
• 3 channels
• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective
Other interval timers
• 16-bit timer: 3 channels (U-TIMER)
• PWM timer: 4 channels
• Watchdog timer: 1 channel
Bit search module
First bit transition “1” or “0” from MSB can be detected in 1 cycle
Interrupt controller
• External interrupt input: Non-maskable interrupt (NMI), normal interrupt × 4 (INT0 to INT3)
• Internal interrupt incident:UART, DMA controller (DMAC), 10-bit A/D converter, 16-bit reload-timer, PWM timer,
U-TIMER and delayed interrupt module
• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)
Others
• Reset cause: Power-on reset/software reset/external reset
• Low-power consumption mode: Sleep mode/stop mode
• Clock control
Gear function: Operating clocks for CPU and peripherals are independently selective
Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
(However, operating frequency for peripherals is less than 25 MHz.)
• Packages: LQFP-100 and QFP-100
• CMOS technology (0.5 µm)
• Power supply voltage: 3.15 V 3.6 V
s PRODUCT LINEUP
Parameter
Classification
Flash size
IRAM size
CROM size
CRAM size
RAM size
I$
Other
Part number
MB91F109
Mass production products Flash
(mask ROM products)
254 Kbytes
2 Kbytes
2 Kbytes
Under trial manufacture
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MB91F109
s PIN ASSIGNMENT
(Top view)
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
VCC
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0/PA0
NMI
VCC
RST
VSS
MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD/P83
WR0/P84
WR1/P85
D16/P20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(FPT-100P-M05)
75 AN3
74 AN2
73 AN1
72 AN0
71 AVSS/AVRL
70 AVRH
69 AVCC
68 A24/EOP0/P70
67 A23/P67
66 A22/P66
65 VSS
64 A21/P65
63 A20/P64
62 A19/P63
61 A18/P62
60 A17/P61
59 A16/P60
58 A15/P57
57 A14/P56
56 A13/P55
55 A12/P54
54 A11/P53
53 A10/P52
52 A09/P51
51 A08/P50
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(Top view)
MB91F109
CS0H/PB2
DW0/PB3
RAS1/PB4/EOP2
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
VCC
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0/PA0
NMI
VCC
RST
VSS
MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD/P83
WR0/P84
WR1/P85
D16/P20
D17/P21
D18/P22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 SO0/TRG1/PF1
79 SI0/TRG0/PF0
78 AN3
77 AN2
76 AN1
75 AN0
74 AVSS/AVRL
73 AVRH
72 AVCC
71 A24/EOP0/P70
70 A23/P67
69 A22/P66
68 VSS
67 A21/P65
66 A20/P64
65 A19/P63
64 A18/P62
63 A17/P61
62 A16/P60
61 A15/P57
60 A14/P56
59 A13/P55
58 A12/P54
57 A11/P53
56 A10/P52
55 A09/P51
54 A08/P50
53 A07/P47
52 A06/P46
51 A05/P45
(FPT-100P-M06)
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