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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16504-3E
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F356B/355A/354A/V350A
DESCRIPTION
The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC
CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which
require high CPU performance for
This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of
single-chip oriented microcontrollers incorporating a wealth of peripheral resources.
The FR60 family is optimized for embedded control applications requiring high processing power of the CPU,
such as DVD player, navigation, high performance Fax machine, and printer controls.
FEATURES
1. FR CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)
• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
• Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store in-
structions
PACKAGE
(Continued)
176-pin plastic LQFP
(FPT-176P-M02)
I2C license
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system
provided that the system conforms to the I2C Standard Specification as defined by Philips.
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MB91350A Series
• Register interlock functions: Facilitating coding in assemblers
• On-chip multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC, PS save): 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• FR family instruction compatible
2. Bus Interface
• Maximum operating frequency: 25 MHz
• Capable of up to 24-bit address full output (16 MB of space)
• 8,16-bit data output
• Built-in pre-fetch buffer
• Non-used data and address pin are usable as general I/O port.
• Capable of chip-select signal output for completely independent four areas settable in 64 KB minimum
• Support for various memory interfaces:
SRAM, ROM/Flash,
page mode Flash ROM, page mode ROM
• Basic bus cycle: 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
• RDY input for external wait cycles
• Support for fly-by transfer for DMA, which enables wait control of independent I/O
3. Mounted Memory
Memory
MB91V350A
ROM
No
RAM (stack)
16 KB
RAM (executable)
16 KB
MB91F355A
512 KB
16 KB
8 KB
MB91F356B
256 KB
16 KB
8 KB
MB91355A
512 KB
16 KB
8 KB
MB91354A
384 KB
8 KB
8 KB
4. DMAC (DMA Controller)
• Capable of simultaneous operation of up to 5 channels (3 channels for externalexternal operation)
• Three transfer sources (external pin, internal peripheral, software) selectable by software. (Transfer can be
started from UART0/1/2.)
• Addressing using 32-bit full addressing mode (increment, decrement, fixed)
• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
• Support for fly-by transfer (between external I/O and memory)
• Selectable transfer data size: 8, 16, or 32-bit
• Multi-byte transfer enabled (by software)
• DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H)
5. Bit Search Module (for REALOS)
• Search for the position of the bit 1/0-changed first in 1 word from the MSB
6. Various Timers
• 4 channels of 16-bit reload timer (including 1 channel for REALOS):
Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3)
• 16-bit free-running timer: 1 channel.
Output compare module: 8 channels. Input capture module: 4 channels
• 16-bit PPG timer 6 channels
7. UART
• UART Full duplex double buffer 5 channel
• Selectable parity On/Off
• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
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MB91350A Series
(Continued)
• Internal timer for dedicated baud rate
• External clock can be used as transfer clock
• Assorted error detection functions (for parity, frame, and overrun errors)
• 115 Kbps support
8. SIO
• 3 channels for 8-bit data serial transfer
• Shift clock selectable from among internal three and external one
• Shift direction selectable (transfer from LSB or MSB) selectable
9. Interrupt Controller
• Total of 17 external interrupt lines (1 nonmaskable interrupt pin and 16 normal interrupt pins available for Wake
Up from STOP)
• interrupt from internal peripheral
• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. D/A Converter
• 8-bit resolution. 3 channels
11. A/D Converter
• 10-bit resolution. 12 channels
• Casting time for serial/parallel conversion: 1.48 µs
• Conversion mode (single conversion mode, continuous conversion mode)
• Activation source (software, external trigger, peripheral interrupt)
12. Other Interval Timer/Counter
• 8/16-bit up/down counter
• 16-bit PPG timer 5 channels
• Watch dog timer
13. I2C Bus Interface (400 Kbps supported)
• 1channel master/slave sending and receiving
• Arbitration and clock synchronization
14. I/O Port
• 3 V I/O ports (16 ports shared for external interrupts support 5 V input.)
• Max 126 ports
15. Other Features
• Internal oscillator circuit as clock source, allowing PLL multiplication to be selected
• Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the
INIT pin is reset.)
• others, watch-dog timer reset, software reset enable
• Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation
at 32 kHz.
• Gear function
• Built-in time base timer
• Package: LQFP-176 (lead pitch: 0.50 mm)
• CMOS technology(0.35 µm)
• Power supply voltage: 3.3 V ± 0.3 V
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MB91350A Series
PIN ASSIGNMENT
(TOP VIEW)
PG5/SCK5
NMI
X1A
VSS
X0A
MD2
MD1
MD0
X0
VCC
X1
INIT
VSS
VCC
PC0/DREQ2
PC1/DACK2
PC2/DSTP2/DEOP2
PB0/DREQ0
PB1/DACK0
PB2/DSTP0/DEOP0
PB3/DREQ1
PB4/DACK1
PB5/DSTP1/DEOP1
PB6/IOWR
PB7/IORD
PA0/CS0
PA1/CS1
PA2/CS2
PA3/CS3
VSS
VCC
P80/IN0/RDY
P81/IN1/BGRNT
P82/IN2/BRQ
P83/RD
P84/WR0
P85/IN3/WR1
P90/SYSCLK
P91
P92/MCLK
P93
P94/AS
VSS
VCC
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
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(FPT-176P-M02)
88 PM1/SO6/BIN0/TRG1
87 PM0/SI6/AIN0/TRG0
86 PN5/PPG5
85 PN4/PPG4
84 PN3/PPG3
83 PN2/PPG2
82 PN1/PPG1
81 PN0/PPG0
80 VCC
79 VSS
78 PO7/OC7
77 PO6/OC6
76 PO5/OC5
75 PO4/OC4
74 PO3/OC3
73 PO2/OC2
72 PO1/OC1
71 PO0/OC0
70 PP3/TOT3
69 PP2/TOT2
68 PP1/TOT1
67 PP0/TOT0
66 VCC
65 VSS
64 AVSS/AVRL
63 AVRH
62 AVCC
61 AN11
60 AN10
59 AN9
58 AN8
57 AN7
56 AN6
55 AN5
54 AN4
53 AN3
52 AN2
51 AN1
50 AN0
49 DA2
48 DA1
47 DA0
46 DAVC
45 DAVS

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MB91350A Series
PIN DESCRIPTION
Pin no.
Pin name
Circuit
type
Description
D16 to D23
External data bus bit 16 to bit 23. Enabled in external bus mode.
1 to 8
C
P20 to P27
Available as a port in external bus 8-bit mode.
D24 to D31
external data bus bit 24 to bit 31. Enabled in external bus mode.
9 to 16
C
P30 to P37
Usable as port at single chip mode.
A00 to A07
19 to 26
P40 to P47
Bits 0 to 7 of external address bus. Enabled in external bus mode.
C
Usable as port at single chip mode.
A08 to A15
27 to 34
P50 to P57
Bits 8 to 15 of external address bus. Enabled in external bus mode.
C
Usable as port at single chip mode.
A16 to A20
37 to 41
P60 to P64
Bits 16 to 20 of external address bus. Enabled in external bus mode.
C Available as a port either in single chip mode or with no external address bus in
use.
A21 to A23
42 to 44
P65 to P67
Bits 21 to 23 of external address bus. Enabled in external bus mode.
C Available as a port either in single chip mode or with no external address bus in
use.
47 to 48 DA0, DA1 D/A converter output pin.
49 DA2 D/A converter output pin.
50 to 57 AN0 to AN7 G Analog input pin.
58 to 61 AN8 to AN11 G Analog input pin.
TOT0 to TOT3
Reload timer output port. This function is enabled when timer output is enabled.
67 to 70
PP0 to PP3
D
General purpose input/output port. This function is enabled when the timer out-
put function is disabled.
OC0
Output compare pin.
71
PO0
D General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
OC1
Output compare pin.
72
PO1
D General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
OC2
Output compare pin.
73
PO2
D General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
OC3 to OC7
Output compare pin.
74 to 78
PO3 to PO7
D
General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
PPG0
PPG timer output pin.
81
PN0
D General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.
(Continued)
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