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FEATURES
Internal key storage for HDCP
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports HDCP 1.1
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TVs
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9380 offers designers the flexibility of an analog
interface and high definition multimedia interface (HDMI)
receiver integrated on a single chip. Also included is support for
high bandwidth digital content protection (HDCP).
The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and FPD resolutions up to SXGA
(1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8 V and 3.3 V power supplies, analog input, and HSYNC .
Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
An on-chip PLL generates a pixel clock from HSYNC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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Analog/HDMI
Dual-Display Interface
AD9380
FUNCTIONAL BLOCK DIAGRAM
R/G/B OR YPbPrIN0
R/G/B OR YPbPrIN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
SCL
SDA
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DDCSDA
DDCSCL
ANALOG INTERFACE
2:1
MUX
CLAMP
R/G/B 8 × 3
A/D
OR YCbCr
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
HDMI RECEIVER
R/G/B 8 × 3
OR YCbCr
2 DATACK
DE
HSYNC
VSYNC
4
HDCP
HDCP KEYS
Figure 1.
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2 DATACK
HSOUT
VSOUT
SOGOUT
DE
S/PDIF
8-CHANNEL
I2S
SCLK
MCLK
LRCLK
AD9380
Pixel clock output frequencies range from 12 MHz to 150 MHz.
PLL clock jitter is typically less than 700 ps p-p at 150 MHz.
The AD9380 also offers full sync processing for composite sync
and sync-on-green (SOG) applications.
The AD9380 contains an HDMI 1.1-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9380 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of the authentication during transmission, as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9380 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

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AD9380
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Specifications..................................................................................... 3
Analog Interface Electrical Characteristics............................... 3
Digital Interface Electrical Characteristics ............................... 4
Absolute Maximum Ratings............................................................ 6
Explanation of Test Levels ........................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Design Guide................................................................................... 12
General Description................................................................... 12
Digital Inputs .............................................................................. 12
Analog Input Signal Handling.................................................. 12
HSYNC and VSYNC Inputs...................................................... 12
Serial Control Port ..................................................................... 12
Output Signal Handling............................................................. 12
Clamping ..................................................................................... 12
Timing.......................................................................................... 16
HDMI Receiver........................................................................... 20
DE Generator .............................................................................. 20
4:4:4 to 4:2:2 Filter ...................................................................... 20
Audio PLL Setup......................................................................... 21
Audio Board Level Muting........................................................ 21
Timing Diagrams........................................................................ 22
REVISION HISTORY
10/05—Revision 0: Initial Version
2-Wire Serial Register Map ........................................................... 23
2-Wire Serial Control Register DetailS........................................ 37
Chip Identification ..................................................................... 37
PLL Divider Control .................................................................. 37
Clock Generator Control .......................................................... 37
Input Gain ................................................................................... 38
Input Offset ................................................................................. 38
Sync .............................................................................................. 39
Coast and Clamp Controls........................................................ 39
Status of Detected Signals ......................................................... 39
Polarity Status ............................................................................. 40
BT656 Generation ...................................................................... 44
Macrovision................................................................................. 45
Color Space Conversion ............................................................ 46
2-Wire Serial Control Port ............................................................ 53
Data Transfer via Serial Interface............................................. 53
Serial Interface Read/Write Examples ..................................... 54
PCB Layout Recommendations.................................................... 55
Analog Interface Inputs ............................................................. 55
Power Supply Bypassing ............................................................ 55
PLL ............................................................................................... 55
Outputs (Both Data and Clocks).............................................. 56
Digital Inputs .............................................................................. 56
Color Space Converter (CSC) Common Settings...................... 57
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 59
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AD9380
SPECIFICATIONS
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Full-Scale Matching
Offset Adjustment Range
SWITCHING PERFORMANCE1
Maximum Conversion Rate
Minimum Conversion Rate
Data-to-Clock Skew
SERIAL PORT TIMING
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS, 5 V TOLERANT
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle, DATACK
Output Coding
Temp
Test Level Min
AD9380KSTZ-100
Typ Max
8
25°C I
25°C I
Full I
−0.6 +1.6/−1.0
±1.0 ±2.1
Guaranteed
Full VI
Full VI 1.0
25°C V
25°C V
25°C VI
Full VI
Full V
0.5
100
0.2
1.25 5
1.50 7
50
Full VI 100
Full VI
Full IV −0.5
10
+2.0
Full VI 4.7
Full VI 4.0
Full VI 0
Full VI 4.7
Full VI 4.0
Full VI 250
Full VI 4.7
Full VI 4.0
Full VI 15
Full VI 100
Full IV
25°C IV
Full IV
110
12
700
15
Full VI 2.6
Full VI
Full V
Full V
25°C V
0.8
−82
82
3
Full VI VDD − 0.1
Full VI
0.4
Full V 45
50 55
Binary
AD9380KSTZ-150
Min Typ Max
8
±0.7 +1.8/−1.0
±1.1 ±2.25
Guaranteed
0.5
1.0
220
1
1.25 5
1.50 7
50
150
10
−0.5 +2.0
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15 110
150
12
700
15
2.6
0.8
−82
82
3
VDD − 0.1
45
50
Binary
0.4
55
Unit
Bits
LSB
LSB
VDD
V p–p
V p–p
ppm/°C
μA
%FS
%FS
%FS
MSPS
MSPS
ns
μs
μs
μs
μs
μs
ns
μs
μs
kHz
MHz
MHz
ps p-p
ps/°C
V
V
μA
μA
pF
V
V
%
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AD9380
Parameter
POWER SUPPLY
VD Supply Voltage
DVDD Supply Voltage
VDD Supply Voltage
PVDD Supply Voltage
ID Supply Current (VD)
IDVDD Supply Current (DVDD)
IDD Supply Current (VDD)2
IPVDD Supply Current (PVDD)
Total Power
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth,
Full Power
Signal–to–Noise Ratio (SNR)
Without Harmonics
fIN = 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θJA Junction-to-Ambient
AD9380KSTZ-100
Temp Test Level Min
Typ Max
Full IV 3.15
Full IV 1.7
Full IV 1.7
Full IV 1.7
25°C VI
25°C VI
25°C VI
25°C VI
Full VI
Full VI
3.3 3.47
1.8 1.9
3.3 3.47
1.8 1.9
260 300
45 60
37 1003
10 15
1.1 1.4
130
25°C V
25°C I
Full V
Full V
V
330
46
45
60
35
1 Drive strength = high.
2 DATACK load = 15 pF, data load = 5 pF.
3 Specified current and power values with a worst-case pattern (on/off).
AD9380KSTZ-150
Min Typ Max
3.15 3.3 3.47
1.7 1.8 1.9
1.7 3.3 3.47
1.7 1.8 1.9
330
85
1303
20
1.15 1.4
130
330
46
45
60
35
Unit
V
V
V
V
mA
mA
mA
mA
W
mW
MHz
dB
dB
dBc
°C/W
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 2.
Parameter
RESOLUTION
DC DIGITAL I/O SPECIFICATIONS
High-Level Input Voltage (VIH)
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH)
Low-Level Output Voltage (VOL)
DC SPECIFICATIONS
Output High Level
IOHD (VOUT = VOH)
Output Low Level
IOLD (VOUT = VOL)
DATACK High Level
VOHC (VOUT = VOH)
DATACK Low Level
VOLC (VOUT = VOL)
Differential Input Voltage, Single-
Ended Amplitude
Test
Level Conditions
VI
VI
VI
VI
IV Output drive = high
IV Output drive = low
IV Output drive = high
IV Output drive = low
IV Output drive = high
IV Output drive = low
IV Output drive = high
IV Output drive = low
IV
AD9380KSTZ-100 AD9380KSTZ-150
Min Typ Max Min Typ Max Unit
8 8 Bit
2.5
VDD − 0.1
VDD − 0.1
2.5
0.8
0.1
V
0.8 V
V
0.1 V
36 36 mA
24 24 mA
12 12 mA
8 8 mA
40 40 mA
20 20 mA
30 30 mA
15 15 mA
75
700 75
700 mV
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AD9380
Parameter
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
DVDD Supply Voltage
PVDD Supply Voltage
IVD Supply Current (Typical Pattern)1
IVDD Supply Current (Typical Pattern)2
IDVDD Supply Current (Typical Pattern)1, 4
IPVDD Supply Current (Typical Pattern)1
Power-Down Supply Current (IPD)
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew
(TDPS)
Channel to Channel Differential Input
Skew (TCCS)
Low-to-High Transition Time for Data and
Controls (DLHT)
Test
Level
IV
IV
IV
IV
V
V
V
V
VI
IV
IV
IV
Low-to-High Transition Time for
DATACK (DLHT)
IV
IV
High-to-Low Transition Time for Data and
Controls (DHLT)
IV
IV
High-to-Low Transition Time for
DATACK (DHLT)
IV
IV
Clock-to-Data Skew5 (TSKEW)
Duty Cycle, DATACK5
DATACK Frequency (FCIP)
IV
IV
IV
VI
Conditions
AD9380KSTZ-100 AD9380KSTZ-150
Min Typ Max Min Typ Max Unit
3.15 3.3 3.47 3.15 3.3 3.47 V
1.7 3.3 347 1.7 3.3 347 V
1.7 1.8 1.9 1.7 1.8 1.9 V
1.7 1.8 1.9 1.7 1.8 1.9 V
80 100
80 110 mA
40 1003
55 1753
88 110
110 145 mA
26 35
30 40 mA
130 130 mA
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
–0.5
45
20
+2.0 −0.5
50
360 ps
6 Clock
Period
900 ps
1300 ps
650 ps
1200 ps
850 ps
1250 ps
800 ps
1200 ps
+2.0 ns
55 %
150 MHz
1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst-case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
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