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ST93C46A,46C,46T
ST93C47C,47T
www.datasheet4u.com
1K (64 x 16 or 128 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 64 x 16 or 128 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
mAUTO-ERASE
oREADY/BUSY SIGNAL DURING
PROGRAMMING
.cSINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST93C46 version
– 3V to 5.5V for ST93C47 version
USEQUENTIAL READ OPERATION
t45ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
ePERFORMANCE for ”C” VERSION
ST93C46A, ST93C46C, ST93C46T,
eST93C47C, ST93C47T are replaced by the
M93C46
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
hDESCRIPTION
SThis specification covers a range of 1K bit serial
taEEPROM products, the ST93C46A,46C,46T
specified at 5V±10% and the ST93C47C,47T
specified at 3V to 5.5V.
aIn the text, products are referred to as ST93C46.
The ST93C46 is a 1K bit Electrically Erasable
.DProgrammableMemory (EEPROM) fabricated with
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
wthrough a serial input (D) and output (Q).
wTable 1. Signal Names
wS Chip Select Input
D
C
S
ORG
VCC
ST93C46
ST93C47
Q
D
Q
C
ORG
VCC
VSS
Serial Data Input
Serial Data Output
Serial Clock
Organisation Select
Supply Voltage
Ground
June 1997
This is information on a product still in production bu t not recommended for new de signs.
wwVSwS .DataSheAIe008t714C 1U/13.com

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ST93C46A/46C/46T, ST93C47C/47T
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
www.datasheet4TuA.com Ambient Operating Temperature
Value
–40 to 125
Unit
°C
TSTG Storage Temperature
–65 to 150
°C
TLEAD Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
VIO Input or Output Voltages (Q = VOH or Hi-Z)
–0.3 to VCC +0.5
V
VCC
VESD
Supply Voltage
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
ST93C46A,T
ST93C46C
ST93C46
–0.3 to 6.5
2000
4000
500
V
V
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 ).
3. EIAJ IC-121 (Condition C) (200pF, 0 ).
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93C46
ST93C47
S1
C2
8 VCC
7 DU
D3
6 ORG
Q4
5 VSS
AI00872C
Warning: DU = Don’t Use
Figure 2C. SO, 90° Turn, Pin Connections
DU
VCC
S
C
ST93C46T
ST93C47T
18
27
36
45
AI00982B
ORG
VSS
Q
D
Warning: DU = Don’t Use
2/13
ST93C46
ST93C47
S1
C2
8 VCC
7 DU
D3
6 ORG
Q4
5 VSS
AI00874C
Warning: DU = Don’t Use
DESCRIPTION (cont’d)
The 1K bit memory is divided into either 128 x 8 bit
bytes or 64 x 16 bit words. The organization may
be selected by a signal on the ORG input. The
memory is accessed by a set of instructions which
includes Read a byte/word, Write a byte/word,
Erase a byte/word, Erase All and Write All.
A Read instruction loads the address of the first
byte/word to be read into an internal address
pointer. The data is then clocked out serially.
The address pointer is automatically incremented
after the data is output and, if the Chip Select input
(S) is held High, the ST93C46 can output a sequen-
tial stream of data bytes/words. In this way, the
memory can be read as a data stream from 8 to
1024 bits long, or continuously as the address

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ST93C46A/46C/46T, ST93C47C/47T
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
www.datasIhnepeut4t uP.ucolsme Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
20ns
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 3. AC Testing Input Output Waveforms
2.4V
0.4V
2V
1V
INPUT
OUTPUT
2.0V
0.8V
AI00815
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
Test Condition
VIN = 0V
VOUT = 0V
Min
Max
Unit
5 pF
5 pF
Table 4. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol
Parameter
Test Condition
ILI Input Leakage Current
0V VIN VCC
ILO Output Leakage Current
0V VOUT VCC,
Q in Hi-Z
Supply Current (TTL Inputs)
ICC
Supply Current (CMOS Inputs)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
ICC1 Supply Current (Standby)
S = VSS, C = VSS,
ORG = VSS or VCC
VIL Input Low Voltage (D, C, S)
VCC = 5V ± 10%
3V VCC 4.5V
VIH Input High Voltage (D, C, S)
VCC = 5V ± 10%
3V VCC 4.5V
VOL Output Low Voltage
IOL = 2.1mA
IOL = 10 µA
VOH Output High Voltage
IOH = –400µA
IOH = –10µA
Min
–0.3
–0.3
2
0.8 VCC
2.4
VCC – 0.2
Max
±2.5
±2.5
3
2
50
0.8
0.2 VCC
VCC + 1
VCC + 1
0.4
0.2
Unit
µA
µA
mA
mA
µA
V
V
V
V
V
V
V
V
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ST93C46A/46C/46T, ST93C47C/47T
Table 5. AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
www.datasheSeyt4mu.bcooml Alt
Parameter
tSHCH
tCSS Chip Select High to Clock High
Test Condition
Min Max Unit
50 ns
tCLSH
tDVCH
tSKS Clock Low to Chip Select High
tDIS Input Valid to Clock High
100 ns
100 ns
tCHDX
tDIH Clock High to Input Transition
Temp. Range: grade 1
Temp. Range:
grades 3, 6
100
200
ns
ns
tCHQL
tCHQV
tPD0 Clock High to Output Low
tPD1 Clock High to Output Valid
500 ns
500 ns
tCLSL
tCSH Clock Low to Chip Select Low
0 ns
tSLCH
tSLSH
Chip Select Low to Clock High
tCS Chip Select Low to Chip Select High
Note 1
250
250
ns
ns
tSHQV
tSLQZ
tSV Chip Select High to Output Valid
tDF Chip Select Low to Output Hi-Z
ST93C46A
ST93C46C, 47C
500 ns
300 ns
200 ns
tCHCL
tSKH Clock High to Clock Low
Note 2
250
ns
tCLCH
tSKL Clock Low to Clock High
Note 2
250
ns
tW tWP Erase/Write Cycle time
10 ms
fC fSK Clock Frequency
0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
tCLSH
tCHCL
C
tSHCH
tCLCH
S
tDVCH
tCHDX
D
START
OP CODE
OP CODE
START
OP CODE INPUT
AI01428
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ST93C46A/46C/46T, ST93C47C/47T
Figure 5. Synchronous Timing, Read or Write
www.datasheet4u.com
C
S
tDVCH
tCHDX
D An
A0
Hi-Z
Q
tCHQL
tCHQV
Q15/Q7
tCLSL
tSLSH
tSLQZ
Q0
ADDRESS INPUT
C
S
tDVCH
D An
Hi-Z
Q
tCHDX
A0/D0
ADDRESS/DATA INPUT
DATA OUTPUT
AI00820C
tSLCH
tCLSL
tSLSH
tSHQV tSLQZ
BUSY
READY
tW
WRITE CYCLE
AI01429
DESCRIPTION (cont’d)
counter automatically rolls over to ’00’ when the
highest address is reached.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 8 or 16 bits at one
time into one of the 128 bytes or 64 words. After
the start of the programming cycle a Busy/Ready
signal is available on the Data output (Q) when
Chip Select (S) is High.
An internal feature of the ST93C46 provides
Power-on Data Protection by inhibiting any opera-
tion when the Supply is too low. The design of the
ST93C46 and the High Endurance CMOS technol-
ogy used for its fabrication give an Erase/Write
cycle Endurance of 1,000,000 cycles and a data
retention of 40 years.
The DU (Don’t Use) pin does not affect the function
of the memory and it is reserved for use by SGS-
THOMSON during test sequences.The pin may be
left unconnected or may be connected to VCC or
VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
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