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Data Sheet
Mixed-Signal Front-End (MxFE) Baseband
Transceiver for Broadband Applications
AD9863
FEATURES
Receive path includes dual 12-bit, 50 MSPS analog-to-digital
converters with internal or external reference
Transmit path includes dual 12-bit, 200 MSPS digital-to-
analog converters with 1×, 2×, or 4× interpolation and
programmable gain control
Internal clock distribution block includes a programmable
phase-locked loop and timing generation circuitry,
allowing single-reference clock operation
24-pin flexible I/O data interface allows various interleaved
or noninterleaved data transfers in half-duplex mode and
interleaved data transfers in full-duplex mode
Configurable through register programmability or
optionally limited programmability through mode pins
Independent Rx and Tx power-down control pins
64-lead LFCSP package (9 mm × 9 mm footprint)
APPLICATIONS
Broadband access
Broadband LAN
Communications (modems)
VIN+A
VIN–A
VIN+B
VIN–B
IOUT+A
IOUT–A
IOUT+B
IOUT–B
FUNCTIONAL BLOCK DIAGRAM
ADC
ADC
DATA
MUX
AND
LATCH
Rx DATA
DAC
DAC
LOW-PASS
INTERPOLATION
FILTER
I/O
INTERFACE
CONFIGURATION
BLOCK
DATA
LATCH
AND
DEMUX
Tx DATA
ADC CLOCK
DAC CLOCK
CLOCK
GENERATION
BLOCK
PLL
AD9863
Figure 1.
I/O
INTERFACE
CONTROL
FLEXIBLE
I/O BUS
[0:23]
CLKIN1
CLKIN2
GENERAL DESCRIPTION
The AD9863 is a member of the MxFE family—a group of
integrated converters for the communications market. The
AD9863 integrates dual 12-bit analog-to-digital converters
(ADC) and dual 12-bit digital-to-analog converters (TxDAC®).
The AD9863 ADCs are optimized for ADC sampling of 50 MSPS
and less. The dual TxDACs operate at speeds up to 200 MHz
and include a bypassable 2× or 4× interpolation filter. The
AD9863 is optimized for high performance, low power, and
small form factor to provide a cost-effective solution for the
broadband communications market.
The AD9863 uses a single input clock pin (CLKIN) or two
independent clocks for the Tx path and the Rx path. The ADC
and TxDAC clocks are generated within a timing generation
block that provides user programmable options such as divide
circuits, PLL multipliers, and switches.
A flexible, bidirectional 24-bit I/O bus accommodates a variety
of custom digital back ends or open market DSPs.
In half-duplex systems, the interface supports 24-bit parallel
transfers or 12-bit interleaved transfers. In full-duplex systems,
the interface supports a 12-bit interleaved ADC bus and a
12-bit interleaved TxDAC bus. The flexible I/O bus reduces pin
count, also reducing the required package size on the AD9863
and the device to which it connects.
The AD9863 can use either mode pins or a serial programma-
ble interface (SPI) to configure the interface bus, operate the
ADC in a low power mode, configure the TxDAC interpolation
rate, and control ADC and TxDAC power-down. The SPI
provides more programmable options for both the TxDAC path
(for example, coarse and fine gain control and offset control for
channel matching) and the ADC path (for example, the internal
duty cycle stabilizer and twos complement data format).
The AD9863 is packaged in a 64-lead LFCSP (low profile, fine
pitched, chip scale package). The 64-lead LFCSP footprint is
only 9 mm × 9 mm and is less than 0.9 mm high, fitting into
such tightly spaced applications as PCMCIA cards.
Rev. B
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Tel: 781.329.4700 ©2003–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9863
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ........................................................................... 2
Tx Path Specifications...................................................................... 3
Rx Path Specifications...................................................................... 4
Power Specifications......................................................................... 5
Digital Specifications........................................................................ 5
Timing Specifications....................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
REVISION HISTORY
4/2017—Rev. A to Rev. B
Changes to Figure 3 and Table 8..................................................... 8
Updated Outline Dimensions ....................................................... 42
Changes to Ordering Guide .......................................................... 42
4/2005—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 40
11/2003—Revision 0: Initial Version
Data Sheet
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
System Block ............................................................................... 18
Rx Path Block.............................................................................. 18
Tx Path Block.............................................................................. 20
Digital Block................................................................................ 23
Programmable Registers............................................................ 33
Clock Distribution Block .......................................................... 36
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
Rev. B | Page 2 of 40

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Data Sheet
AD9863
Tx PATH SPECIFICATIONS
FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB; AVDD = DVDD = 3.3 V,
unless otherwise noted.
Table 1.
Parameter
Tx PATH GENERAL
Resolution
Maximum DAC Update Rate
Maximum Full-Scale Output Current
Full-Scale Error
Gain Mismatch Error
Offset Mismatch Error
Reference Voltage
Output Capacitance
Phase Noise (1 kHz Offset, 6 MHz Tone)
Output Voltage Compliance Range
TxPGA Gain Range
TxPGA Step Size
Tx PATH DYNAMIC PERFORMANCE
(IOUTFS = 20 mA; FOUT = 1 MHz)
SNR
SINAD
THD
SFDR, Wide Band (DC to Nyquist)
SFDR, Narrow Band (1 MHz Window)
Temp
Full
Full
Full
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
Test Level
IV
IV
IV
V
IV
IV
V
V
V
IV
V
V
Full IV
Full IV
Full IV
Full IV
Full IV
Min Typ Max Unit
12
200
20
1%
3.5 +3.5
0.1 +0.1
1.23
5
115
1.0 +1.0
20
0.10
Bits
MHz
mA
% FS
% FS
V
pF
dBc/Hz
V
dB
dB
70.8 71.6
dB
64.3 71
dB
79 66.3 dBc
68.5 77
dBc
72.8 81
dBc
1 See Figure 2 for description of the TxDAC termination scheme.
TxDAC
50
50
Figure 2. Diagram Showing Termination of 100 Ω Differential
Load for Some TxDAC Measurements
Rev. B | Page 3 of 40

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AD9863
Data Sheet
RX PATH SPECIFICATIONS
FADC = 50 MSPS; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter
Rx PATH GENERAL
Resolution
Maximum ADC Sample Rate
Gain Mismatch Error
Offset Mismatch Error
Reference Voltage
Reference Voltage (REFT–REFB) Error
Input Resistance (Differential)
Input Capacitance
Input Bandwidth
Differential Analog Input Voltage Range
Rx PATH DC ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Aperture Delay
Aperture Uncertainty (Jitter)
Input Referred Noise
AD9863 Rx PATH DYNAMIC PERFORMANCE
(VIN = –0.5 dBFS; FIN = 10 MHz)
SNR
SINAD
THD (Second to Ninth Harmonics)
SFDR, Wide Band (DC to Nyquist)
Crosstalk Between ADC Inputs
Temp Test Level Min
Typ
Max Unit
Full V
Full IV
Full V
Full V
Full V
Full IV
Full V
Full V
Full V
Full V
12
50
±0.2
±0.1
1.0
30 ±6
2
5
30
2
Bits
MSPS
% FS
% FS
V
+30 mV
kΩ
pF
MHz
V p-p differential
25°C V
25°C V
25°C V
25°C V
25°C V
±0.75
±0.75
2.0
1.2
250
LSB
LSB
ns
ps rms
µV
Full V
Full V
Full IV
Full IV
Full V
67
65.5
73
68.3 74
80
66.6
dBc
dBc
dBc
dBc
dB
Rev. B | Page 4 of 40

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Data Sheet
AD9863
POWER SPECIFICATIONS
Analog and digital supplies = 3.3 V; FCLKIN1 = FCLKIN2 = 50 MHz; PLL 4× setting; normal timing mode.
Table 3.
Parameter
POWER SUPPLY RANGE
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Driver Supply Voltage (DRVDD)
ANALOG SUPPLY CURRENTS
Tx Path (20 mA Full-Scale Outputs)
Tx Path (2 mA Full-Scale Outputs)
Rx Path (50 MSPS)
Rx Path (50 MSPS, Low Power Mode)
Rx Path (20 MSPS, Low Power Mode)
Tx Path, Power-Down Mode
Rx Path, Power-Down Mode
PLL
DIGITAL SUPPLY CURRENTS
Tx Path, 1× Interpolation,
50 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
Tx Path, 2× Interpolation,
100 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
Tx Path, 4× Interpolation,
200 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
Rx Path Digital, Half-Duplex 24 Mode
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
V
V
V
V
V
V
V
V
V
Full V
Full V
Full V
Min Typ Max Unit
2.7 3.6 V
2.7 3.6 V
2.7 3.6 V
70 mA
20 mA
103 mA
69 mA
55 mA
2 mA
5 mA
12 mA
20 mA
50 mA
80 mA
15 mA
DIGITAL SPECIFICATIONS
Table 4.
Parameter
LOGIC LEVELS
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Output Logic High Voltage, VOH (1 mA Load)
Output Logic Low Voltage, VOL (1 mA Load)
DIGITAL PIN
Input Leakage Current
Input Capacitance
Minimum RESET Low Pulse Width
Digital Output Rise/Fall Time
Temp Test Level
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Min
DRVDD 0.7
DRVDD 0.6
5
2.8
Typ Max Unit
V
0.4 V
V
0.4 V
12 µA
3 pF
Input clock cycles
4 ns
Rev. B | Page 5 of 40