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FEATURES
95 MSPS maximum conversion rate
9% or less p-p PLL clock jitter at 95 MSPS
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsyncs counter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCD TV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9980 is a complete, 8-bit, 95 MSPS, monolithic analog
interface optimized for capturing YPbPr video and RGB
graphics signals. Its 95 MSPS encode rate capability and full-
power analog bandwidth of 200 MHz supports all HDTV
video modes and graphics resolutions up to XGA (1024 × 768
at 85 Hz).
The AD9980 includes a 95 MHz triple ADC with an internal
reference, a phase-locked loop (PLL), programmable gain,
offset, and clamp controls. The user provides only 3.3 V and
1.8 V power supplies and an analog input. Three-state CMOS
outputs may be powered from 1.8 V to 3.3 V.
The AD9980’s on-chip PLL generates a sample clock from
the three-level sync (for YPbPr video) or the horizontal sync
(for RGB graphics). Sample clock output frequencies range from
10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at
95 MSPS.
High Performance
8-Bit Display Interface
AD9980
FUNCTIONAL BLOCK DIAGRAM
PR/REDIN1
PR/REDIN0
Y/GREENIN1
Y/GREENIN0
PB/BLUEIN1
PB/BLUEIN0
2:1
MUX
2:1
MUX
2:1
MUX
8 AUTO OFFSET
CLAMP
PGA
8-BIT
ADC
8
8 AUTO OFFSET
AD9980
8
CB/CR/REDOUT
CLAMP
PGA
8-BIT
ADC
8
8 AUTO OFFSET
8
Y/GREENOUT
CLAMP
PGA
8-BIT
ADC
8
8
CB/BLUEOUT
HSYNC1
HSYNC2
VSYNC1
VSYNC2
SOGIN1
SOGIN2
EXTCLK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
Figure 1.
DTACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFCM
REFLO
With internal Coast generation, the PLL maintains its output
frequency in the absence of sync input. A 32-step sampling
clock phase adjustment is provided. Output data, sync, and
clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The AD9980 also
offers full sync processing for composite sync and sync-on-
green applications. A clamp signal is generated internally or
may be provided by the user through the CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9980 is
provided in a space-saving, 80-pin, Pb-free, LQFP surface
mount plastic package. It is specified over the 0°C to +70°C
temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.

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AD9980
TABLE OF CONTENTS
Analog Interface specifications....................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels........................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Design Guide................................................................................... 10
General Description................................................................... 10
Digital Inputs .............................................................................. 10
Input Signal Handling................................................................ 10
Hsync and Vsync Inputs............................................................ 10
Serial Control Port ..................................................................... 10
Output Signal Handling............................................................. 10
Clamping ..................................................................................... 10
Gain and Offset Control............................................................ 11
Timing Diagrams........................................................................ 19
Hsync Timing ............................................................................. 20
Coast Timing............................................................................... 20
Output Formatter ....................................................................... 20
Two-Wire Serial Register Map...................................................... 22
Detailed 2-Wire Serial Control Register Descriptions .............. 28
Chip Identification ..................................................................... 28
PLL Divider Control .................................................................. 28
Clock Generator Control .......................................................... 28
Phase Adjust................................................................................ 29
Input Gain ................................................................................... 29
Input Offset ................................................................................. 29
Hsync Controls ........................................................................... 29
Vsync Controls ........................................................................... 30
Coast and Clamp Controls........................................................ 31
SOG Control ............................................................................... 33
Input and Power Control........................................................... 33
Output Control ........................................................................... 34
Sync Processing .......................................................................... 35
Detection Status.......................................................................... 36
Polarity Status ............................................................................. 36
Hsync Count ............................................................................... 37
Two-Wire Serial Control Port....................................................... 38
Data Transfer via Serial Interface............................................. 38
PCB Layout Recommendations ............................................... 40
PLL ............................................................................................... 40
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
1/05—Initial Version: Revision 0
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AD9980
ANALOG INTERFACE SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VD = 3.3 V, VDD = 3.3 V, PVD = 1.8 V, DAVDD = 1.8 V, ADC clock = maximum conversion rate, full temperature range = 0°C to 70°C.
Table 1.
Parameter
RESOLUTION
Number of Bits
LSB Size
DC ACCURACY
Differential Nonlinearity
80 MSPS Conversion Rate
Differential Nonlinearity
95 MSPS Conversion Rate
Integral Nonlinearity
80 MSPS Conversion Rate
Integral Nonlinearity
95 MSPS Conversion Rate
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Full-Scale Matching
Offset Adjustment Range
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew tSKEW
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS3
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
Temp
AD9980KSTZ-801
Test Level Min
Typ Max Min
AD9980KSTZ-952
Typ Max
88
0.39 0.39
25°C I
Full VI
25°C I
Full VI
25°C I
Full VI
25°C I
Full VI
25°C I
Full VI
Full VI
25°C V
25°C V
Full V
Full VI
Full VI
Full VI
Full IV
Full IV
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full IV
25°C IV
Full IV
Full IV
Full VI
Full VI
Full V
Full V
25°C V
0.2 0.75
0.2 1.0
±0.3 ±1.0
±0.3 ±1.3
Guaranteed
0.2 0.75
0.2 1.0
0.6 1.5
0.75 2.25
±0.3 ±1.0
±0.3 ±1.3
±0.6 ±2.25
±0.9 ±3.2
Guaranteed
0.5
1.0 1.0
105
1
1
19
44
80 95
10
−0.5 +2 −0.5
4.7 4.7
4.0 4.0
00
4.7 4.7
4.0 4.0
250 250
4.7 4.7
4.0 4.0
80 95
10
750
15
2.5 2.5
0.8
–82
82
2
0.5
105
1
1
1 10
44
10
+2
10
980
15
0.8
–82
82
2
Unit
Bits
% of
Full
Scale
LSB
LSB
LSB
LSB
LSB
V p-p
V p-p
ppm/°C
µA
µA
% FS
% FS
MSPS
MSPS
ns
µs
µs
µs
µs
µs
Ns
µs
µs
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
µA
µA
pF
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AD9980
Parameter
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle, DATACK
Output Coding
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
DAVD Supply Voltage
ID Supply Current (VD)
IDD Supply Current (VDD)4
IPVD Supply Current (PVD)
IDAVD Supply Current (DAVD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Crosstalk
THERMAL CHARACTERISTICS
θJC, Junction-to-Case
Thermal Resistance
θJA, Junction-to-Ambient
Thermal Resistance
Temp
AD9980KSTZ-801
Test Level Min
Typ Max Min
AD9980KSTZ-952
Typ Max
Full VI
Full VI
Full IV
VDD − 0.2
50
Binary
0.2
VDD − 0.1
0.1
50
Binary
Full IV
Full IV
Full IV
Full IV
25°C V
25°C V
25°C V
25°C V
Full VI
Full VI
Full VI
3.13 3.3 3.47 3.13
1.7 3.3 3.47 1.7
1.7 1.8 1.9 1.7
1.7 1.8 1.9 1.7
233
42
11
10
953 1070
18 27
55 81
3.3 3.47
3.3 3.47
1.8 1.9
1.8 1.9
240
49
8
12
993 1114
18 28
55 88
25°C V
Full V
200
60
200
60
V 16
16
V 35
35
1 Output drive strength = 0 was used for all 80 MHz parameters.
2 Output drive strength = 1 was used for all 95 MHz parameters.
3 Digital inputs are HSYNC0, HSYNC1, VSYNC0, VSYNC1, SDA, SCL, EXTCLK, CLAMP, and PWRDN.
4 DATACK load = 10 pF, data load = 5 pF.
Unit
V
V
%
V
V
V
V
mA
mA
mA
mA
mW
mA
mW
MHz
dBc
°C/W
°C/W
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VD
VDD
PVD
DAVDD
Analog Inputs
REFHI
REFCM
REFLO
Digital Inputs
Digital Output Current
Functional Temperature
Storage Temperature
Maximum Junction Temperature
Rating
3.6 V
3.6 V
1.98 V
1.98 V
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to + 85°C
−65°C to + 150°C
150°C
AD9980
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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