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93AA86A/B/C, 93LC86A/B/C,
93C86A/B/C
16K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range
93AA86A
93AA86B
93LC86A
93LC86B
93C86A
93C86B
93AA86C
93LC86C
93C86C
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
PE Pin
No
No
No
No
No
No
Yes
Yes
Yes
Features:
• Low-power CMOS technology
• ORG pin to select word size for ‘86C’ version
• 2048 x 8-bit organization ‘A’ devices (no ORG)
• 1024 x 16-bit organization ‘B’ devices (no ORG)
• Program Enable pin to write-protect the entire
array (‘86C’ version only)
• Self-timed erase/write cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported:
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Pin Function Table
Name
Function
CS
CLK
DI
DO
VSS
PE
ORG
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Memory Configuration
Power Supply
Word Size
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8 or 16-bit
8 or 16-bit
8 or 16-bit
Temp Ranges
I
I
I, E
I, E
I, E
I, E
I
I, E
I, E
Packages
OT
OT
OT
OT
OT
OT
P, SN, ST, MS, MC
P, SN, ST, MS, MC
P, SN, ST, MS, MC
Description:
The Microchip Technology Inc. 93XX86A/B/C devices
are 16K bit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX86C are dependent upon external logic
levels driving the ORG pin to set word size. In the
SOT-23 package, the 93XX86A devices provide
dedicated 8-bit memory organization, while the
93XX86B devices provide dedicated 16-bit memory
organization. A Program Enable (PE) pin allows the
user to write-protect the entire memory array.
Advanced CMOS technology makes these devices
ideal for low-power, nonvolatile memory applications.
The entire 93XX Series is available in standard
packages including 8-lead PDIP and SOIC, and
advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. Pb-free
(Pure Matte Sn) finish is available.
Package Types (not to scale)
PDIP/SOIC
(P, SN)
SOT-23
(OT)
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 PE
6 ORG
5 VSS
DO 1
VSS 2
DI 3
6 VCC
5 CS
4 CLK
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 PE
6 ORG
5 VSS
CS 1
CLK 2
DI 3
DO 4
DFN
(MC)
8 VCC
7 PE
6 ORG
5 VSS
© 2005 Microchip Technology Inc.
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93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V
Param.
No.
Symbol
Parameter
Min Typ Max Units
Conditions
D1 VIH1 High-level input voltage
2.0 — VCC +1 V VCC 2.7V
VIH2
0.7 VCC — VCC +1 V VCC < 2.7V
D2 VIL1 Low-level input voltage
VIL2
-0.3 — 0.8
V VCC 2.7V
-0.3 — 0.2 VCC V VCC < 2.7V
D3 VOL1 Low-level output voltage
VOL2
— — 0.4 V IOL = 2.1 mA, VCC = 4.5V
— — 0.2 V IOL = 100 μA, VCC = 2.5V
D4 VOH1 High-level output voltage 2.4 —
VOH2
VCC - 0.2 —
V IOH = -400 μA, VCC = 4.5V
V IOH = -100 μA, VCC = 2.5V
D5 ILI
Input leakage current
— — ±1 μA VIN = VSS or VCC
D6 ILO
Output leakage current
— — ±1 μA VOUT = VSS or VCC
D7 CIN, Pin capacitance (all inputs/ —
COUT outputs)
D8 ICC write Write current
—7
—3
500 —
pF VIN/VOUT = 0V (Note 1)
TA = 25°C, FCLK = 1 MHz
mA FCLK = 3 MHz, VCC = 5.5V
μA FCLK = 2 MHz, VCC = 2.5V
D9 ICC read Read current
D10 ICCS
Standby current
— — 1 mA FCLK = 3 MHz, VCC = 5.5V
— — 500 μA FCLK = 2 MHz, VCC = 3.0V
— 100 —
μA FCLK = 2 MHz, VCC = 2.5V
— — 1 μA I – Temp
— — 5 μA E – Temp
CLK = CS = 0V
ORG = DI
PE = VSS or VCC
(Note 2) (Note 3)
D11 VPOR VCC voltage detect
— 1.5 —
— 3.8 —
(Note 1)
V 93AA86A/B/C, 93LC86A/B/C
V 93C86A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG and PE pin not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO, see Section 3.4 “Data Out (DO)”.
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93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
TABLE 1-2: AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V
Param.
No.
Symbol
Parameter
Min Max Units
Conditions
A1
FCLK
Clock frequency
A2
TCKH
Clock high time
A3
TCKL
Clock low time
A4
TCSS
Chip Select setup time
A5 TCSH Chip Select hold time
A6
TCSL
Chip Select low time
A7 TDIS Data input setup time
A8 TDIH Data input hold time
A9 TPD Data output delay time
A10 TCZ
A11 TSV
Data output disable time
Status valid time
A12 TWC
Program cycle time
— 3 MHz 4.5V VCC < 5.5V
2 MHz 2.5V VCC < 4.5V
1 MHz 1.8V VCC < 2.5V
200 — ns 4.5V VCC < 5.5V
250 ns 2.5V VCC < 4.5V
450 ns 1.8V VCC < 2.5V
100 — ns 4.5V VCC < 5.5V
200 ns 2.5V VCC < 4.5V
450 ns 1.8V VCC < 2.5V
50 — ns 4.5V VCC < 5.5V
100 ns 2.5V VCC < 4.5V
250 ns 1.8V VCC < 2.5V
0 — ns 1.8V VCC < 5.5V
250 — ns 1.8V VCC < 5.5V
50 — ns 4.5V VCC < 5.5V
100 ns 2.5V VCC < 4.5V
250 ns 1.8V VCC < 2.5V
50 — ns 4.5V VCC < 5.5V
100 ns 2.5V VCC < 4.5V
250 ns 1.8V VCC < 2.5V
— 100 ns 4.5V VCC < 5.5V, CL = 100 pF
250 ns 2.5V VCC < 4.5V, CL = 100 pF
400 ns 1.8V VCC < 2.5V, CL = 100 pF
— 100 ns 4.5V VCC < 5.5V, (Note 1)
200 ns 1.8V VCC < 4.5V, (Note 1)
— 200 ns 4.5V VCC < 5.5V, CL = 100 pF
300 ns 2.5V VCC < 4.5V, CL = 100 pF
500 ns 1.8V VCC < 2.5V, CL = 100 pF
— 5 ms Erase/Write mode (AA and LC
versions)
A13 TWC
A14 TEC
A15 TWL
— 2 ms Erase/Write mode
(93C versions)
— 6 ms ERAL mode, 4.5V VCC 5.5V
— 15 ms WRAL mode, 4.5V VCC 5.5V
A16 —
Endurance
1M — cycles 25°C, VCC = 5.0V, (Note 2)
Note 1:
2:
This parameter is periodically sampled and not 100% tested.
This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from Microchip’s web site
at www.microchip.com.
© 2005 Microchip Technology Inc.
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93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
VIH
CS
VIL
CLK
VIH
VIL
VIH
DI
VIL
TDIS
TCSS
DO
(Read)
VOH
VOL
DO VOH
(Program)
VOL
TSV
TCKH
TDIH
TPD
Note: TSV is relative to CS.
TCKL
Status Valid
TCSH
TPD
TCZ
TCZ
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX86B OR 93XX86C WITH ORG = 1)
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK
Cycles
READ
1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 —
D15-D0
29
EWEN
1 00 1 1 X X X X X X X X
HighZ
13
ERASE
1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13
ERAL
1 00 1 0 X X X X X X X X — (RDY/BSY) 13
WRITE
1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY) 29
WRAL
EWDS
1 00 0 1 X X X X X X X X D15-D0 (RDY/BSY) 29
1 00 0 0 X X X X X X X X
High-Z
13
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX86A OR 93XX86C WITH ORG = 0)
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK
Cycles
READ
EWEN
1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 —
1 00 1 1 X X X X X X X X X
D7-D0
High-Z
22
14
ERASE
1
11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
14
ERAL
1
00
1 0XXXXXXXXX
— (RDY/BSY)
14
WRITE
1
01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/BSY)
22
WRAL
EWDS
1
00
0 1 X X X X X X X X X D7-D0 (RDY/BSY)
22
1 00 0 0 X X X X X X X X X
High-Z
14
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93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG pin (93XX86C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
2.3 Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS
command should be performed after
every write operation and an external 10
kΩ pull-down protection resistor should be
added to the CS pin.
After power-up the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Note:
To prevent accidental writes to the array in
the 93XX86C devices, set the PE pin to a
logic low.
© 2005 Microchip Technology Inc.
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DS21797G-page 5