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ISP1505A; ISP1505C
ULPI Hi-Speed Universal Serial Bus host and peripheral
transceiver
Rev. 01 — 19 October 2006
Product data sheet
1. General description
The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The ISP1505 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1505 can interface to the link with digital I/O voltages in the range of
1.65 V to 3.6 V.
The ISP1505 is available in HVQFN24 package.
2. Features
I Fully complies with:
N Universal Serial Bus Specification Rev. 2.0
N UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I Interfaces to host and peripheral cores; optimized for stand-alone and embedded host
applications with an external VBUS supply; stand-alone peripheral cores, and Session
Request Protocol (SRP)-capable peripheral cores
I Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N USB clock and data recovery to receive USB data at ±500 ppm
N Insertion of stuff bits during transmit and discarding of stuff bits during receive
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I Supports SRP for reduced power consumption
N Complete control over bus resistors
N Data line and VBUS pulsing session request methods
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ISP1505A; ISP1505C
ULPI HS USB host and peripheral transceiver
N Integrated VBUS voltage comparators
I Highly optimized ULPI-compliant interface
N 60 MHz, 8-bit interface between the core and the transceiver
N Supports both 60 MHz input clock and 60 MHz output clock configurations
N Integrated Phase-Locked Loop (PLL) with auto-configuring support for 60 MHz
input clock, or one crystal or clock frequency: 19.2 MHz (ISP1505ABS), 26 MHz
(ISP1505CBS)
N Fully programmable ULPI-compliant register set
N Internal Power-On Reset (POR) circuit
I Flexible system integration and very low current consumption, optimized for portable
devices
N Power-supply input range is 3.0 V to 3.6 V
N Internal voltage regulator supplies 3.3 V and 1.8 V
N Supports external VBUS charge pump
N External VBUS source is controlled using the PSW_N pin; open-drain PSW_N
allows per-port or ganged power control
N FAULT input pin to monitor the external VBUS supply status
N Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage
pins minimize crosstalk
N Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization
N Typical suspend current of 35 µA
I Full industrial grade operating temperature range from 40 °C to +85 °C
I 4 kV ElectroStatic Discharge (ESD) protection on pins DP, DM, VBUS and GND
I Available in a small HVQFN24 (4 mm × 4 mm) Restriction of Hazardous Substances
(RoHS) compliant, halogen-free and lead-free package
3. Applications
I Digital still camera
I Digital TV
I Digital Video Disc (DVD) recorder
I External storage device, for example:
N Zip drive
N Magneto-Optical (MO) drive
N Optical drive: CD-ROM, CD-RW, DVD
I Mobile phone
I MP3 player
I PDA
I Printer
I Scanner
I Set-Top Box (STB)
I Video camera
ISP1505A_ISP1505C_1
Product data sheet
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Rev. 01 — 19 October 2006
© NXP B.V. 2006. All rights reserved.
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NXP Semiconductors
ISP1505A; ISP1505C
ULPI HS USB host and peripheral transceiver
4. Ordering information
Table 1. Ordering information
Part Package
Type number
Marking Crystal or Name
clock
frequency
ISP1505ABS
05A[1]
19.2 MHz HVQFN24
ISP1505CBS
05C[1]
26 MHz HVQFN24
Description
Version
plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4 × 4 × 0.85 mm
plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4 × 4 × 0.85 mm
[1] The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1505A_ISP1505C_1
Product data sheet
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Rev. 01 — 19 October 2006
© NXP B.V. 2006. All rights reserved.
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5. Block diagram
ISP1505A; ISP1505C
ULPI HS USB host and peripheral transceiver
ULPI
INTERFACE
CLOCK
STP
DIR
NXT
DATA
[7:0]
8
21
15
14
16
1, 2,
17 to 20,
22, 24
USB DATA
SERIALIZER
ULPI
INTERFACE
CONTROLLER
USB DATA
DESERIALIZER
REGISTER
MAP
VBUS VALID EXTERNAL
DRIVE VBUS EXTERNAL
HIGH-SPEED
USB ATX
TERMINATION
RESISTORS
6 DP
5 DM
USB
CABLE
RESET_N/
PSW_N
12
POWER-ON
RESET
XTAL1
XTAL2
VCC(I/O)
REG3V3
REG1V8
VCC
GLOBAL
CLOCKS
PLL
10
CRYSTAL
11 OSCILLATOR
3, 23
9
13
interface voltage
internal power
7 VOLTAGE
REGULATOR
Fig 1. Block diagram
GLOBAL
RESET
VBUS
COMPARATORS
SRP CHARGE
AND DISCHARGE
RESISTORS
ISP1505
VREF
BAND GAP
REFERENCE
VOLTAGE
8
VBUS/
FAULT
4 RREF
004aaa587
ISP1505A_ISP1505C_1
Product data sheet
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Rev. 01 — 19 October 2006
© NXP B.V. 2006. All rights reserved.
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6. Pinning information
6.1 Pinning
ISP1505A; ISP1505C
ULPI HS USB host and peripheral transceiver
terminal 1
index area
DATA1
DATA0
VCC(I/O)
RREF
DM
DP
1
2
3
4
5
6
ISP1505
18 DATA6
17 DATA7
16 NXT
15 STP
14 DIR
13 REG1V8
004aaa689
Transparent top view
Fig 2. Pin configuration HVQFN24; top view
6.2 Pin description
Table 2. Pin description
Symbol[1][2] Pin Type[3]
DATA1
1 I/O
DATA0
2 I/O
VCC(I/O)
RREF
DM
DP
VCC
VBUS/FAULT
3
4
5
6
7
8
P
AI/O
AI/O
AI/O
P
AI/O
REG3V3
XTAL1
XTAL2
9P
10 AI
11 AO
Description[4]
pin 1 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
pin 0 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
I/O supply rail
resistor reference
data minus (D) pin of the USB cable
data plus (D+) pin of the USB cable
input supply voltage or battery source
This pin has two possible functions:
VBUS (analog input and output) — VBUS pin of the USB cable.
FAULT (input) — Input pin for the external VBUS digital overcurrent or fault detector
signal.
If this pin is not used as either VBUS or FAULT, it must be tied to ground.
5 V tolerant
3.3 V regulator output
crystal oscillator or clock input
crystal oscillator output
ISP1505A_ISP1505C_1
Product data sheet
DataSheet4 U .com
Rev. 01 — 19 October 2006
© NXP B.V. 2006. All rights reserved.
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