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FEATURES
General
HDMITM/DVI transmitter compatible with HDMI v1.2a,
DVI v1.0, and HDCP 1.1
Single 1.8 V power supply
Video/audio inputs accept logic level s from 1.8 V to 3.3 V
76-ball CSP_BGA, Pb-free package
Digital video
80 MHz operation supports all resolutions from 480i to
720p/1080i and XGA-75 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, DDR
Supports ITU656 based embedded syncs
Auto input video format timing detection (CEA-861B)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
8-channel uncompressed LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting S/PDIF
and I2S
On-chip MPU reports HDMI events through interrupts and
registers
APPLICATIONS
DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter
GENERAL DESCRIPTION
The AD9889A-BBCZ is an 80 MHz, high definition multimedia
interface (HDMI) v.1.2a transmitter. It supports HDTV formats
up to 720p/1080i, and computer graphic resolutions up to XGA
(1024 × 768 @ 75 Hz). With the inclusion of HDCP, the AD9889A
allows the secure transmission of protected content as specified
by the HDCP v1.1 protocol.
The AD9889A supports both S/PDIF and 8-channel I2S audio.
Its high fidelity 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
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High Performance
HDMI/DVI Transmitter
AD9889A
FUNCTIONAL BLOCK DIAGRAM
SCL SDA
MCL MDA
INT
CLK
VSYNC
HSYNC
DE
D[23:0]
S/PDIF
MCLK
I2S[3:0]
LRCLK
SCLK
I2C
SLAVE
REGISTER
CONFIGURATION
LOGIC
HDCP
CORE
INTERRUPT
HANDLER
HDCP-EDID
MICRO-
CONTROLLER
I2C
MASTER
VIDEO
DATA
CAPTURE
COLOR
SPACE
CONVER-
SION
4:2:2 TO
4:4:4
CONVER-
SION
XOR
MASK
HDMI
Tx
CORE
AUDIO
DATA
CAPTURE
AD9889A
Figure 1.
HPD
DDCSDA
DDCSCL
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
LPCM audio or compressed audio including Dolby® Digital,
DTS®, and THX®.
The AD9889A helps to reduce system design complexity and
cost by incorporating such features as an internal MPU for
HDCP operations, an I2C master for EDID reading, a single
1.8 V power supply and 5 V tolerance on I2C and hot plug
detect pins.
Fabricated in an advanced CMOS process, the AD9889A
is available in a space saving, 76-ball, CSP_BGA surface-
mount package. The CSP_BGA package is specified from
−25°C to +90°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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AD9889A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Explanation of Test Levels ........................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Applications........................................................................................7
Design Resources ..........................................................................7
Document Conventions ...............................................................7
PCB Layout Recommendations.......................................................8
Power Supply Bypassing ...............................................................8
Digital Inputs .................................................................................8
External Swing Resistor................................................................8
Output Signals ...............................................................................8
Outline Dimensions ..........................................................................9
Ordering Guide..............................................................................9
REVISION HISTORY
10/06—Revision 0: Initial Version
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AD9889A
SPECIFICATIONS
Table 1.
Parameter
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case
θJA Junction-to-Ambient
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current, IIL
Input Clamp Voltage
Differential High Level Output Voltage
Differential Output Short-Circuit Current
POWER SUPPLY
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Power-Down Current
Transmitter Supply Current2
Transmitter Total Power
AC SPECIFICATIONS
CLK Frequency
TMDS Output CLK Duty Cycle
Worst Case CLK Input Jitter
Input Data Setup Time
Input Data Hold Time
TMDS Differential Swing
VSYNC and HSYNC Delay from DE Falling Edge
VSYNC and HSYNC Delay to DE Rising Edge
DE High Time
DE Low Time
Differential Output Swing
Low-to-High Transition Time
High-to-Low Transition Time
AUDIO AC TIMING
Sample Rate
I2S Cycle Time
I2S Setup Time
I2S Hold Time
Audio Pipeline Delay
Conditions
−16 mA
+16 mA
With active video applied
80 MHz, typical random pattern
I2S and S/PDIF
Temp
Full
Full
25°C
Full
Full
Full
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Test Level1
VI
VI
V
VI
VI
V
V
V
VI
V
V
V
IV
IV
V
IV
IV
VI
IV
IV
IV
IV
IV
VI
VI
VI
VI
VI
VII
VII
IV
IV
IV
IV
IV
Min
1.4
VDD − 0.1
−25
−10
1.71
13.5
48
1
1
800
75
75
32
Typ
3
15.2
59
+25
−0.8
+0.8
AVCC
1.8
9
143
257
1000
1
1
138
15
0
75
Max
0.7
0.4
+90
+10
10
1.89
50
155
280
80
52
2
1200
8191
490
490
192
1
Unit
V
V
pF
V
V
°C/W
°C/W
°C
μA
V
V
V
μA
V
mV p-p
mA
mA
mW
MHz
%
ns
ns
ns
mV
UI3
UI
UI
UI
ps
ps
kHz
UI
ns
ns
μs
1 See Explanation of Test Levels section.
2 Using low output drive strength.
3 UI = unit interval.
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AD9889A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Digital Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
Rating
5 V to 0.0 V
20 mA
−40°C to +90°C
−65°C to +150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design
and characterization testing.
VII. Limits defined by HDMI specification; guaranteed by
design and characterization testing.
ESD CAUTION
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AD9889A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
BOTTOM VIEW
(Not to Scale)
Figure 2. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type1
A1 to A10, B1
to B10, C9,
C10, D9, D10
D[23:0]
I
D1 CLK I
C2 DE I
C1
HSYNC
I
D2
VSYNC
I
J3
EXT_SW
I
K3 HPD I
E2
S/PDIF
I
E1
MCLK
I
F2, F1, G2, G1 I2S[3:0]
I
H2
SCLK
I
H1
LRCLK
I
J7
PD/A0
I
K1, K2
TxC−/TxC+ O
K10, J10
Tx2−/Tx2+ O
K7, K8
Tx1−/Tx1+ O
K4, K5
Tx0−/Tx0+ O
H10 INT O
J2, J5, J8, K9 AVDD
D5, D6, D7, E7 DVDD
P
P
G4, G5, J1
PVDD
P
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
GND
P
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to
5.0 V CMOS logic level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips
digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level.
I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available
through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the
PD/A0 pin state when the supplies are applied to the AD9889A. 1.8 V to 3.3 V CMOS logic level.
Differential Clock Output. Differential clock output at pixel clock rate; transition minimized
differential signaling (TMDS) logic level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS
logic level.
Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate;
TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS
logic level.
Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is
recommended.
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic
and I/Os. They should be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the AD9889A is the clock generation
circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free
power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889A be
assembled on a single, solid ground plane with careful attention given to ground current paths.
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