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Data Sheet
June 14, 2005
ISL6269
FN9177.0
Single Phase PWM Controller for Mobile
Graphical Processing Unit (GPU)
The ISL6269 IC is a Single-Phase Synchronous-Buck PWM
controller featuring Intersil's Robust Ripple Regulator (R3)
technology that delivers truly superior dynamic response to
input voltage and output load transients. Integrated
MOSFET drivers, 5V LDO, and bootstrap diode result in
fewer components and smaller implementation area.
Intersil’s R3 technology combines the best features of fixed-
frequency PWM and hysteretic PWM while eliminating many
of their shortcomings. R3 technology employs an innovative
modulator that synthesizes an AC ripple voltage signal VR,
analogous to the output inductor ripple current. The AC
signal VR enters a hysteretic comparator where the lower
threshold is the error amplifier output VCOMP, and the upper
threshold is a programmable voltage reference VW, resulting
in generation of the PWM signal. The voltage reference VW
sets the steady-state PWM frequency. Both rising and falling
edges of the PWM are modulated, providing faster response
to input voltage transients and output load transients than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, the ISL6269 has an error
amplifier that provides ±1% voltage regulation at the FB pin.
The ISL6269 has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269
can be configured to operate in forced-continuous-
conduction-mode (FCCM) or in diode-emulation-mode
(DEM), which improves light-load efficiency. In FCCM the
controller always operates as a synchronous rectifier,
switching the low-side MOSFET regardless of the output
load, however with DEM enabled, the low-side MOSFET is
disabled preventing negative current flow from the output
inductor during low load operation. An audio filter prevents
the PWM switching frequency from entering the audible
spectrum due to extremely light load while in DEM.
A PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The ISL6269 features a unique
fault-identification capability that can drastically reduce
trouble-shooting time and effort. The pull-down resistance of
the PGOOD pin is 30for an overcurrent fault, 60for an
overvoltage fault, or 90for either an undervoltage fault or
during soft-start. The overcurrent protection is accomplished
by measuring the voltage drop across the rDS(ON) of the
low-side MOSFET. A single resistor programs the
overcurrent and short-circuit points. Overvoltage and
undervoltage protection is monitored at the FB voltage
feedback pin.
Features
• High performance synthetic ripple regulation
• Extremely fast transient response
• External type-two loop compensation
• ±1% regulation accuracy: -10°C to +100°C
• Starts into a pre-biased output
• Wide input voltage range: +7.0V to +25.0V
• Wide output voltage range: +0.6V to +3.3V
• Wide output load range: 0A to 25A
• Programmable PWM frequency: 200kHz to 600kHz
• Power good monitor
• Fault identification by PGOOD pull down resistance
• Integrated MOSFET drivers with shoot-through protection
• Internal digital soft-start
• Internal 5V LDO regulator
• Configure forced continuous conduction or diode
emulation for increased light load efficiency
• PWM minimum frequency above audible spectrum
• Integrated boot-strap diode
• Low-side MOSFET rDS(ON) overcurrent protection
• Undervoltage protection
• Soft crowbar overvoltage protection
• Over-temperature protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
16 LD QFN (4mm x 4mm)
TOP VIEW
16 15 14 13
VIN 1
VCC 2
FCCM 3
EN 4
GND
12 PVCC
11 LG
10 PGND
9 ISEN
5678
ISL6269
Ordering Information
PART NUMBER TEMP (°C)
PACKAGE PKG. DWG. #
ISL6269CRZ
(See Note)
-10 to +100 16 Ld 4x4 QFN
(Pb-Free)
L16.4x4
ISL6269CRZ-T
(See Note)
16 Ld 4x4 QFN Tape and Reel
(Pb-Free)
L16.4x4
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2 FN9177.0
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ISL6269
Absolute Voltage Ratings
ISEN, VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VCC, PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, FCCM. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
. . . . . . . . . . . . . . . . . . . . . . . . . . (<100ns Pulse Width, 10µJ) -5.0V
BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UG. . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . (<200ns Pulse Width, 20µJ) -4.0V
LG . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . (<100ns Pulse Width, 4µJ) -2.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . .Level 1 (HBM = 2kV)
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package . . . . . . . . . . . . . . . . . . .
43
11.5
Junction Temperature Range . . . . . . . . . . . . . . . . . -55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . -10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . (soldering, 10s)+300°C
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . -10°C to 100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 7V to 25V
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a highly effective thermal conductivity test board on free air. See Tech Brief TB379 for details
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
These specifications apply for VIN = 15V, TA = (-10°C) to (+100°C), unless otherwise stated.
All typical specifications TA = ( + 2 5 ° C )
SYMBOL
TEST CONDITIONS
MIN TYP
VIN
VIN Voltage Range
VIN Input Bias Current
VIN Shutdown Current
VCC LDO
VIN
IVIN
ISHDN
EN and FCCM = 5V, FB = 0.65V, VIN = 7V to 25V
EN = GND, VIN = 25V
7.0
2.2
0.1
VCC Output Voltage Range
VCC POR THRESHOLD
VCC
VIN = 7V to 25V, ILDO = 0mA to 80mA
4.75 5.00
Rising VCC POR Threshold Voltage
Falling VCC POR Threshold Voltage
REGULATION
VCCTHR
VCCTHF
4.35 4.45
4.10 4.20
Error Amplifier Reference Voltage
Voltage Regulation Accuracy
PWM
VREF
VREG
0.6
-1
Frequency Range
Frequency-Set Accuracy
VO Range
VO Input Leakage Current
FOSC
FAUDIO
VVO
IVO
FCCM = 5V
FCCM = GND
FOSC = 300kHz
VO = 0.60V
VO = 3.30V
200
21 28
-12
0.60
1.3
7.0
ERROR AMPLIFIER
FB Input Bias Current
COMP Source Current
COMP Sink Current
COMP High Clamp Voltage
COMP Low Clamp Voltage
IFB
ICOMPSRC
ICOMPSNK
VCOMPHC
VCOMPLC
FB = 0.60V
FB = 0.40V, COMP = 3.20V
FB = 0.80V, COMP = 0.30V
FB = 0.40V, Sink 50µA
FB = 0.80V, Source 50µA
3.10
0.09
± 20
2.5
0.3
3.40
0.15
MAX
25.0
3.0
1.0
5.25
4.55
4.30
+1
600
+12
3.30
3.65
0.21
UNIT
V
mA
µA
V
V
V
V
%
kHz
kHz
%
V
µA
µA
nA
mA
mA
V
V
3 FN9177.0
June 14, 2005

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ISL6269
Electrical Specifications
PARAMETER
These specifications apply for VIN = 15V, TA = (-10°C) to (+100°C), unless otherwise stated.
All typical specifications TA = ( + 2 5 ° C ) ( C o n t i n u e d )
SYMBOL
TEST CONDITIONS
MIN TYP
POWER GOOD
PGOOD Pull Down Impedance
PGOOD Leakage Current
PGOOD Maximum Sink Current
PGRSS
PGRUV
PGROV
PGROC
IPGOOD
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5mA Sink
PGOOD = 5V
80 95
53 63
26 32
<0.1
5.0
PGOOD Soft-Start Delay
GATE DRIVER
TSS EN High to PGOOD High
2.20 2.75
UG Pull-Up Resistance
UG Source Current
UG Sink Resistance
UG Sink Current
LG Pull-Up Resistance
LG Source Current
LG Sink Resistance
LG Sink Current
Delay From UG Falling to LG Rising
Delay From LG Falling to UG Rising
BOOTSTRAP DIODE
RUGPU
IUGSRC
RUGPD
IUGSNK
RLGPU
ILGSRC
RLGPD
ILGSNK
tUGFLGR
tLGFUGR
200mA Source Current (Note 2)
VUG to PHASE = 2.5V
250mA Sink Current (Note 2)
VUG to PHASE = 2.5V
250mA Source Current (Note 2)
VLG to PGND = 2.5V
250mA Sink Current (Note 2)
VLG to PGND = 2.5V
UG falling to LG rising
LG falling to UG rising
1.0
2.0
1.0
2.0
1.0
2.0
0.5
4.0
21
14
Forward Voltage
Reverse Leakage
CONTROL INPUTS
VF PVCC = 5V, IF = 2mA
IR VR = 25V
0.58
0.2
EN High Threshold Voltage
EN Low Threshold Voltage
FCCM High Threshold Voltage
FCCM Low Threshold Voltage
EN Leakage Current
FCCM Leakage Current
PROTECTION
VENTHR
VENTHF
VFCCMTHR
VFCCMTHF
IENL
EN = 0V
IENH
EN = 5.0V
IFCCML FCCM = 0V
IFCCMH FCCM = 5.0V
2.0
2.0
<0.1
20
<0.1
2.0
ISEN OCP Threshold Current
ISEN Short-Circuit Threshold Current
UVP Threshold Voltage
OVP Rising Threshold Voltage
OVP Falling Threshold Voltage
OTP Rising Threshold Temperature
OTP Temperature Hysteresis
NOTE:
3. Guaranteed by design.
IOC
ISC
VUV
VOVR
VOVF
TOTR
TOTHYS
(Note 2)
(Note 2)
-33 -26
-50
81 84
113 116
103
150
25
MAX
133
89
46
1.0
3.30
1.5
1.5
1.5
0.9
0.5
1.0
1.0
1.0
-19
87
119
UNIT
µA
mA
ms
A
A
A
A
ns
ns
V
µA
V
V
V
V
µA
µA
µA
µA
µA
µA
%
%
%
°C
°C
4 FN9177.0
June 14, 2005

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ISL6269
Functional Pin Descriptions
GND Pin
Bottom terminal pad of QFN package
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
VIN Pin-1 (Input)
The VIN pin measures the converter input voltage with
respect to the GND pin. VIN is a required input to the R3
PWM modulator. The VIN pin is also the input source for the
integrated +5V LDO regulator.
VCC Pin-2 (Output)
The VCC pin is the output of the integrated +5V LDO
regulator, which provides the bias voltage for the IC. The
VCC pin delivers regulated +5V whenever the EN pin is
pulled above VENTHR. For best performance the LDO
requires at least a 1µF MLCC decouple capacitor to the
GND pin.
FCCM Pin-3 (Logic)
The FCCM pin configures the controller to operate in forced-
continuous-conduction-mode (FCCM) or diode-emulation-
mode (DEM.) DEM is disabled when the FCCM pin is pulled
above the rising threshold voltage VFCCMTHR, and DEM is
enabled when the FCCM pin is pulled below the falling
threshold voltage VFCCMTHF.
EN Pin-4 (Logic)
The EN pin is the on/off switch of the IC. When the EN pin is
pulled above the rising threshold voltage VENTHR, VCC will
ramp up and begin regulation. The soft-start sequence
begins once VCC ramps above the power-on reset (POR)
rising threshold voltage VCCTHR. When the EN pin is pulled
below the falling threshold voltage VENTHF, PWM
immediately stops and VCC decays below the POR falling
threshold voltage VCCTHF, at which time the IC turns off.
COMP Pin-5 (Signal)
The COMP pin is the output of the control-loop error
amplifier. Loop compensation components connect from the
COMP pin to the FB pin.
FB Pin-6 (Signal)
The FB pin is the inverting input of the control loop error
amplifier. The converter will regulate to 600mV at the FB pin
with respect to the GND pin. Scale the desired output
voltage to 600mV with a voltage divider network made from
resistors RTOP and RBOTTOM. Loop compensation
components connect from the FB pin to the COMP pin.
FSET Pin-7 (Signal)
The FSET pin programs the PWM switching frequency of the
converter. Connect a resistor RFSET and a 10nF capacitor
CFSET from the FSET pin to the GND pin.
VO Pin-8 (Input)
The VO pin makes a direct measurement of the converter
output voltage used exclusively by the R3 PWM modulator.
The VO pin should be connected to the top of feedback
resistor RTOP at the converter output. Refer to Figure 1,
Typical Application Schematic.
ISEN Pin-9 (Input)
The ISEN pin is the input to the overcurrent protection (OCP)
and short-circuit protection (SCP) circuits. Connect a resistor
RSEN between the ISEN pin and the PHASE pin. Select the
value of RSEN that will force the ISEN pin to source the ISEN
threshold current IOC when the peak inductor current
reaches the desired OCP setpoint. The SCP threshold
current ISC is fixed at twice the OCP threshold current IOC
PGND Pin-10
The PGND pin should be connected to the source of the low-
side MOSFET, preferably with an isolated path that is in
parallel with the trace connecting the LG pin to the gate of
the MOSFET. The PGND pin is an isolated path used
exclusively to conduct the turn-off transient current that flows
out the PGND pin, through the gate-source capacitance of
the low-side MOSFET, into the LG pin, and back to the
PGND pin through the pull-down resistance of the LG driver.
The adaptive shoot-through protection circuit, measures the
low-side MOSFET gate voltage with respect to the PGND
pin, not the GND pin.
LG Pin-11 (Output)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC Pin-12 (Input)
The PVCC pin is the input voltage for the low-side MOSFET
gate driver LG. Connect a +5V power source to the PVCC
pin with respect to the GND pin, a 1µF MLCC bypass
capacitor needs to be connected from the PVCC pin to the
PGND pin, not the GND pin. The VCC output may be used
for the PVCC input voltage source. Connect the VCC pin to
the PVCC pin through a low-pass filter consisting of a
resistor and the PVCC bypass capacitor. Refer to Figure 1,
Typical Application Schematic.
5 FN9177.0
June 14, 2005