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Data Sheet
October 16, 2006
ISL6264
FN6359.1
Two-Phase Core Controller for AMD
Mobile Turion CPUs
The ISL6264 is a two-phase buck converter regulator with
embedded gate drivers. The two-phase buck converter uses
two interleaved channels to effectively double the output
voltage ripple frequency and thereby reduce output voltage
ripple amplitude with fewer components, lower component
cost, reduced power dissipation, and smaller real estate
area. ISL6264 can also be configured as single-phase
controller for low power CPU applications.
The heart of the ISL6264 is the patented R3 Technology,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technologyhas the fastest transient response. This is due
to the R3 modulator commanding variable switching
frequency during a load transient.
To boost battery life, the ISL6264 supports PSI_L for deeper
sleep mode via automatically enabling different operation
modes. At heavy load operation of the active mode, the
regulator commands the two phase continuous conduction
mode (CCM) operation. While the PSI_L is asserted during
the deeper sleep mode, the ISL6264 smoothly disables one
phase and operates in a one-phase diode emulation mode
(DE) to maximize the efficiency at light load.
A 6-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.375V to 1.55V.
A 0.5% system accuracy of the core output voltage over
temperature at active mode is achieved by the ISL6264.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per AMD mobile CPU
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
Features
• Precision Two-phase Core Voltage Regulator
- 0.5% system accuracy over temperature
• Voltage positioning with Adjustable Load Line and Offset
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Differential Current Sensing: DCR or resistor
• Microprocessor Voltage Identification Input
- 6-Bit VID Input
- 0.775V to 1.55V in 12.5mV Steps
- 0.375V to 0.7625V in 25mV Steps
• Adjustable Reference-Voltage Offset
• Audio Filter Enable/Disable
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
Ordering Information
PART
NUMBER
(Note)
PART
PACKAGE PKG.
MARKING TEMP (°C) (Pb-Free) DWG. #
ISL6264CRZ ISL6264CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
ISL6264CRZ-T ISL6264CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6264
ISL6264
(40 LD 6x6 QFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
SET 1
RBIAS 2
OFS 3
SOFT 4
OCSET 5
VW 6
COMP 7
FB 8
VDIFF 9
VSEN 10
GND PAD
(BOTTOM)
30 UGATE1
29 PHASE1
28 PGND1
27 LGATE1
26 PVCC
25 LGATE2
24 PGND2
23 PHASE2
22 UGATE2
21 BOOT2
11 12 13 14 15 16 17 18 19 20
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ISL6264
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . PHASE -0.3V (DC) to BOOT
PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
-2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . -0.3 - +7V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to 150°C junction may trigger the shutdown of
the device even before 150°C, since this number is specified as typical.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
INPUT POWER SUPPLY
IVDD
+5V Supply Current
VR_ON = 3.3V
VR_ON = 0V
- 3.1 3.6 mA
- - 1 µA
IVIN Battery Supply Current at VIN pin
PORr POR (Power-On Reset) Threshold
PORf
SYSTEM AND REFERENCES
%Error System Accuracy
(VDD_core)
VR_ON = 0V, VIN = 25V,
VDD Rising
VDD Falling
No load, closed loop, active mode, TA = +25°C to +100°C,
VID = 0.75-1.55V
VID = 0.425-0.75V
-
-
3.9
-0.5
-2
-
4.35
4.1
-
-
1
4.5
-
0.5
+2
µA
V
V
%
%
VID = 0.375-0.425V
-4 - +4 %
RRBIAS
VDD_core
(max)
RBIAS Voltage
Maximum Output Voltage
RRBIAS = 147k
VID = [000000]
1.5 1.52 1.54
- 1.55 -
V
V
VDD_core Minimum Output Voltage
(min)
VID = [111111]
- 0.375 -
V
CHANNEL FREQUENCY
fSW Nominal Channel Frequency
Adjustment Range
RFSET = 6.81k, 2 channel operation,
Vcomp = 2V
285 300 315 kHz
200 - 500 kHz
AMPLIFIERS
Droop Amplifier Offset
-0.3 0.3 mV
AV0
GBW
Error Amp DC Gain (Note 3)
Error Amp Gain-Bandwidth Product CL = 20pF
(Note 3)
- 90 - dB
- 18 - MHz
SR Error Amp Slew Rate (Note 3)
CL = 20pF
- 5.0 - V/µs
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ISL6264
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
ISEN1, ISEN2
Imbalance Voltage
- - 1 mV
Input Bias Current
- 20 - nA
SOFT START CURRENT
ISS Soft Start Current
I2 Soft Current during VID on the Fly
GATE DRIVER DRIVING CAPABILITY
-48 -43 -38
±185 ±210 ±235
µA
µA
RSRC(UGATE) UGATE Source Resistance (Note 4) 500mA Source Current
ISRC(UGATE) UGATE Source Current (Note 4)
VUGATE_PHASE = 2.5V
RSNK(UGATE) UGATE Sink Resistance (Note 4) 500mA Sink Current
ISNK(UGATE) UGATE Sink Current (Note 4)
VUGATE_PHASE = 2.5V
RSRC(LGATE) LGATE Source Resistance (Note 4) 500mA Source Current
ISRC(LGATE) LGATE Source Current (Note 4)
VLGATE = 2.5V
RSNK(LGATE) LGATE Sink Resistance (Note 4)
500mA Sink Current
ISNK(LGATE) LGATE Sink Current (Note 4)
VLGATE = 2.5V
Rp(UGATE) UGATE to PHASE Resistance
GATE DRIVER SWITCHING TIMING (refer to timing diagram)
- 1 1.5
-2-A
- 1 1.5
-2-A
- 1 1.5
-2-A
- 0.5 0.9
-4-A
- 1 - k
tRU UGATE Rise Time (Note 3)
tRL LGATE Rise Time (Note 3)
tFU UGATE Fall Time (Note 3)
tFL LGATE Fall Time (Note 3)
tPDHU UGATE Turn-on Propagation Delay
tPDHL
LGATE Turn-on Propagation Delay
BOOTSTRAP DIODE
PVCC = 5V, 3nF Load
PVCC = 5V, 3nF Load
PVCC = 5V, 3nF Load
PVCC = 5V, 3nF Load
PVCC = 5V, Outputs Unloaded
PVCC = 5V, Outputs Unloaded
- 8.0 -
- 8.0 -
- 8.0 -
- 4.0 -
23 30 44
7 15 30
ns
ns
ns
ns
ns
ns
Forward Voltage
Leakage
POWER GOOD and PROTECTION MONITOR
VDDP = 5V, Forward Bias Current = 2mA
VR = 16V
0.43 0.58 0.67
- -1
V
µA
VOL
IOH
tpgd
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
IPGOOD = 4mA
PGOOD = 3.3V
VR_ON Enable to PGOOD High when Csoft = 47nF
- 0.11 0.4
-1 -
1
6.3 7.6 8.9
V
µA
ms
OVH
OVHS
Over-voltage Threshold
Severe Over-voltage Threshold
OCSET Reference Current
VO rising above setpoint >1ms
VO rising above setpoint >0.5µs
Rbias = 147k
155 195 235
1.775 1.8 1.825
10 10.2 10.4
mV
V
µA
OC Threshold Offset
DROOP rising above OCSET >120µs
-3 - 3 mV
Current Imbalance Threshold
Difference between ISEN1-ISEN2 >1ms
- 8 - mV
UVf Under-voltage Threshold
(VDIFF-SOFT)
VO falling below setpoint for >1ms
-300 -250 -200 mV
OFFSET FUNCTION
IOFFSET
IFB
OFS Pin Current
FB Pin Souring Current
36.5kresistor connects OFS pin to GND.
- 33 - µA
- 33 - µA
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ISL6264
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
LOGIC INPUTS
VIL(3.3V)
VIH(3.3V)
IIL(3.3V)
IIL(3.3V)
VIL(3.3V)
VIH(3.3V)
IIL(3.3V)
IIL(3.3V)
VIL(1.0V)
VR_ON
VR_ON
Leakage current of VR_ON
SET
SET
Leakage current of SET
DAC(VID0-VID5) and PSI_L input
low
Logic input is low
Logic input is high at 3.3V
Logic input is low
Logic input is high at 3.3V
- -1
2.3 -
-
-1 0
-
- 01
- -1
2.3 -
-
-1 0
-
- 0.45 1
- - 0.3
V
V
µA
µA
V
V
µA
µA
V
VIH(1.0V)
IIL(1V)
DAC(VID0-VID5), PSI_L input high
Leakage current of DAC(VID0-VID5) Logic input is low
and PSI_L
Logic input is high at 1V
0.7 -
-1 0
- 0.45
-
-
1
V
µA
µA
NOTES:
3. Guaranteed by design.
4. Guaranteed by characterization.
ISL6264 Gate Driver Timing Diagram
PWM
tPDHU
UGATE
LGATE
tFL
1V
tRU
tFU
1V
tPDHL
tRL
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