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FEATURES
105 MSPS guaranteed sampling rate (AD9460-105)
79.4 dBFS SNR/91 dBc SFDR with 10 MHz input
(3.4 V p-p input, 80 MSPS)
78.3 dBFS SNR/ with 170 MHz input
(4.0 V p-p input, 80 MSPS)
77.8 dBFS SNR/87 dBc SFDR with 170 MHz input
(3.4 V p-p input, 80 MSPS)
77.2 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 105 MSPS)
90 dBFS two-tone SFDR with 139 MHz/140 MHz input
(3.4 V p-p input, 105 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output data capture clock available
3.3 V and 5 V supply operation
APPLICATIONS
MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9460 operates up to 105 MSPS, providing a superior signal-
to-noise ratio (SNR) for instrumentation, medical imaging, and
radar receivers using baseband (<100 MHz) and IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
16-Bit, 80 MSPS/105 MSPS ADC
AD9460
VIN+
VIN–
CLK+
CLK–
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
AD9460
BUFFER
T/H
CLOCK
AND TIMING
MANAGEMENT
16
PIPELINE
ADC
CMOS
OR
LVDS
OUTPUT
STAGING
2
32
2
REF
DFS
DCS MODE
OUTPUT MODE
OR
D15 TO D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9460 is available in a Pb-free, 100-lead, surface-mount,
plastic package (TQFP_EP) specified over the industrial tem-
perature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. True 16-bit linearity.
2. High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
3. Ease of use: on-chip reference and high input impedance,
track-and-hold with adjustable analog input range, and an
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP/EP.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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AD9460
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
REVISION HISTORY
7/06—Revision 0: Initial Version
Pin Configurations and Function Descriptions ............................8
Equivalent Circuits......................................................................... 12
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 20
Analog Input and Reference Overview ................................... 20
Clock Input Considerations...................................................... 21
Power Considerations................................................................ 22
Digital Outputs ........................................................................... 23
Timing ......................................................................................... 23
Operational Mode Selection ..................................................... 23
Evaluation Board ............................................................................ 24
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Rev. 0 | Page 2 of 32

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AD9460
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal
trimmed reference (1.0 V mode), analog input amplitude = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
VOLTAGE REFERENCE
Output Voltage VREF = 1.7 V
Load Regulation @ 1.0 mA
Reference Input Current (External VREF = 1.7 V)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
VREF = 1.7 V
VREF = 1.0 V
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance2
Input Capacitance2
POWER SUPPLIES
Supply Voltages
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Currents1
AVDD1
AVDD21, 3
IDRVDD1—LVDS Outputs
IDRVDD1—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION3
LVDS Outputs
CMOS Outputs (DC Input)
Temp
Full
AD9460BSVZ-80
Min Typ
Max
16
AD9460BSVZ-105
Min Typ
Max
16
Unit
Bits
Full Guaranteed
Guaranteed
Full
−5.0 ±0.1
+5.0 −5.0 ±0.1
+5.0 mV
25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR
Full −3.4
+3.4 −3.4
+3.4 % FSR
25°C −0.8 ±0.5 +0.8 −0.85 ±0.5 +0.85 LSB
Full −0.9
+0.9 −1
+1.2
25°C −6 ±3
+6 −6 ±3
+6 LSB
Full 1.7
Full ±2
Full 350
25°C 2.4
1.7 V
±2 mV
350 μA
2.5 LSB rms
Full 3.4
3.4 V p-p
Full 2.0
2.0 V p-p
Full 3.5
3.5 V
Full 3.2
3.9 3.2
3.9 V
Full 1
1 kΩ
Full 6
6 pF
Full 3.14 3.3 3.46 3.14 3.3 3.46 V
Full 4.75 5.0 5.25 4.75 5.0 5.25 V
Full 3.0 3.3 3.6 3.0 3.3 3.6 V
Full 3.0 3.3 3.6 3.0 3.3 3.6 V
Full
290 310
337 373 mA
Full
101 110
116 133 mA
Full
70 78.5
71 81 mA
Full 14
14 mA
Full 1
Full 0.2
1 mV/V
0.2 %/V
Full
1.7 1.8
1.9 2.2 W
Full 1.5
1.7 W
1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3 For SFDR = AVDD1, IAVDD2 power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.
Rev. 0 | Page 3 of 32

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AD9460
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal
trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 170 MHz
fIN = 225 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 170 MHz
fIN = 225 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 170 MHz
fIN = 225 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND
OR THIRD HARMONIC)
fIN = 10 MHz
fIN = 170 MHz
fIN = 225 MHz
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS
fIN = 10 MHz
fIN = 170 MHz
fIN = 225 MHz
TWO-TONE SFDR
fIN = 139.6 MHz @ −7 dBFS, 140.6 MHz @ −7 dBFS
ANALOG BANDWIDTH
Temp
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
25°C
Full
AD9460BSVZ-80
Min Typ Max
77.6 78.4
77.4
76.1 76.8
75.0
75.7
76.1 78.0
74.4
74.0 76.1
72.1
74.6
12.8
12.5
12.3
80 91
78
80 87
78
82
94 100
91
90 98
88
97
89
615
AD9460BSVZ-105
Min Typ Max
77.2 78.1
76.9
75.0 76.2
74.5
75.2
75.2 77.4
74.5
72.0 75.1
71.2
73.6
12.7
12.4
12.1
Unit
dB
dB
dB
dB
dB
dB
bits
bits
bits
80 88
76
78 84
74
81
dBc
dBc
dBc
92 98
91
89 98
85
92
90
615
dBc
dBc
dBc
dBFS
MHz
Rev. 0 | Page 4 of 32

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AD9460
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Input Resistance
Input Capacitance
Temp
Full
Full
Full
Full
Full
AD9460BSVZ-80/105
Min Typ Max
2.0
−10
2
0.8
200
+10
Full 3.25
Full
0.2
Full 247
Full 1.125
545
1.375
Full 0.2
Full 1.3 1.5 1.6
Full 1.1 1.4 1.7
Full 2
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
Unit
V
V
μA
μA
pF
V
V
mV
V
V
V
pF
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9460BSVZ-80
Min Typ Max
80
1
12.5
5.0
5.0
3.35
2.3 3.6 4.8
13
60
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
AD9460BSVZ-105
Min Typ Max
105
1
9.5
3.8
3.8
3.35
2.3 3.6 4.8
13
60
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
cycles
ns
fs, rms
Rev. 0 | Page 5 of 32