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10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
FEATURES
Pin-compatible family
Excellent dynamic performance
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
LVDS sampling integrity
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
160-lead chip scale ball grid array (CSP_BGA) package
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 μm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
RESET
S1 S2 S3
IRQ
DACCLK– DACCLK+
SDIO
SDO
CSB
SCLK
C1
SPI CONTROLLER C2
C3 C3
DATACLK_OUT+
DATACLK_OUT–
CLOCK
DISTRIBUTION
S3
DATACLK_IN+
DATACLK_IN–
DB[13:0]+
DB[13:0]–
14-, 12-,
IOUTA
10-BIT DAC
CORE
IOUTB
C2 BAND GAP
C1S1
REFERENCE
CURRENT S2
VREF
I120
Figure 1.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2. Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
3. Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
4. Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5. The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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©2006 Analog Devices, Inc. All rights reserved.

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AD9734/AD9735/AD9736
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
AC Specifications.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Location of Supply and Control Pins....................................... 16
Terminology .................................................................................... 17
Typical Performance Characteristics ........................................... 18
AD9736 Static Linearity, 10 mA Full Scale ............................. 18
AD9736 Static Linearity, 20 mA Full Scale ............................. 19
AD9736 Static Linearity, 30 mA Full Scale ............................. 20
AD9735 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 21
AD9734 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 22
AD9736 Power Consumption, 20 mA Full Scale....................... 23
AD9736 Dynamic Performance, 20 mA Full Scale................ 24
AD9735, AD9734 Dynamic Performance, 20 mA
Full Scale...................................................................................... 27
AD973x WCDMA ACLR, 20 mA Full Scale .......................... 28
SPI Register Map............................................................................. 29
SPI Register Details ........................................................................ 30
Mode Register (Reg. 0) .............................................................. 30
Interrupt Request Register (IRQ) (Reg. 1) .............................. 30
Full Scale Current (FSC) Registers (Reg. 2, Reg. 3)............... 31
LVDS Controller (LVDS_CNT) Registers
(Reg. 4, Reg. 5, Reg. 6) ............................................................... 31
SYNC Controller (SYNC_CNT) Registers
(Reg. 7, Reg. 8)............................................................................ 32
Cross Controller (CROS_CNT) Registers
(Reg. 10, Reg. 11)........................................................................ 32
Analog Control (ANA_CNT) Registers
(Reg. 14, Reg. 15)........................................................................ 33
Built-In Self Test Control (BIST_CNT) Registers
(Reg. 17, Reg. 18, Reg. 19, Reg. 20, Reg. 21)........................... 33
Controller Clock Predivider (CCLK_DIV) Reading
Register (Reg. 22) ....................................................................... 34
Theory of Operation ...................................................................... 35
Serial Peripheral Interface ............................................................. 36
General Operation of the Serial Interface............................... 36
Short Instruction Mode (8-Bit Instruction) ........................... 36
Long Instruction Mode (16-Bit Instruction).......................... 36
Serial Interface Port Pin Descriptions ..................................... 36
SCLK—Serial Clock............................................................... 36
CSB—Chip Select................................................................... 37
SDIO—Serial Data I/O.......................................................... 37
SDO—Serial Data Out .......................................................... 37
MSB/LSB Transfers .................................................................... 37
Notes on Serial Port Operation ................................................ 37
Pin Mode Operation .................................................................. 38
RESET Operation....................................................................... 38
Programming Sequence ............................................................ 38
Interpolation Filter..................................................................... 39
Data Interface Controllers......................................................... 39
LVDS Sample Logic.................................................................... 40
LVDS Sample Logic Calibration............................................... 40
Operating the LVDS Controller in Manual Mode via the
SPI Port ........................................................................................ 41
Rev. A | Page 2 of 72

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Operating the LVDS Controller in Surveillance and
Auto Mode ...................................................................................41
SYNC Logic and Controller...........................................................42
SYNC Logic and Controller Operation....................................42
Operation in Manual Mode.......................................................42
Operation in Surveillance and Auto Modes ............................42
FIFO Bypass.................................................................................42
Digital Built-In Self Test (BIST) ....................................................44
Overview ......................................................................................44
AD973x BIST Procedure............................................................45
AD973x Expected BIST Signatures ..........................................45
Generating Expected Signatures ...............................................46
Cross Controller Registers .............................................................47
Analog Control Registers ...............................................................48
Band Gap Temperature Characteristic Trim Bits ...................48
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................8
Inserted Table 5..................................................................................9
Replaced Pin Configuration and Function Descriptions
Section ..............................................................................................10
Changes to Figure 27 to Figure 38 ................................................21
Changes to Figure 40 ......................................................................23
Changes to Table 9 ..........................................................................29
Changes to Figure 103 ....................................................................56
Changes to Figure 105 ....................................................................58
Changes to Figure 107 ....................................................................60
Changes to Figure 108 ....................................................................61
Changes to Figure 115 ....................................................................68
Updated Outline Dimensions........................................................69
Changes to Ordering Guide...........................................................69
4/05—Revision 0: Initial Version
AD9734/AD9735/AD9736
Mirror Roll-Off Frequency Control .........................................48
Headroom Bits.............................................................................48
Voltage Reference........................................................................48
Applications Information...............................................................50
Driving the DACCLK Input ......................................................50
DAC Output Distortion Sources...................................................51
DC-Coupled DAC Output.............................................................52
DAC Data Sources ..........................................................................53
Input Data Timing ..........................................................................54
Synchronization Timing.................................................................55
Power Supply Sequencing ..............................................................56
AD973X Evaluation Board Schematics ........................................57
AD973X Evaluation Board PCB Layout.......................................62
Outline Dimensions........................................................................69
Ordering Guide ...........................................................................69
Rev. A | Page 3 of 72

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AD9734/AD9735/AD9736
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Offset Error
Gain Error (With Internal
Reference)
Gain Error (Without Internal
Reference)
Full-Scale Output Current
Output Compliance Range
Output Resistance
Output Capacitance
TEMPERATURE DRIFT
Offset
Gain
Reference Voltage1
REFERENCE
Internal Reference Voltage1
Output Resistance2
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
SUPPLY CURRENTS
1× Mode, 1.2 GSPS
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
2× Mode, 1.2 GSPS
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR 2× Interpolation Filter
Enabled
AD9736
AD9735
AD9734
Min Typ
Max Min Typ
Max Min Typ
Max Unit
14 12 10 Bits
−5.6 ±1.0
−2.1 ±0.6
+5.6 −1.5 ±0.50 +1.5 −0.5 ±0.12
+2.1 −0.5 ±0.25 +0.5 −0.1 ±0.06
+0.5 LSB
+0.1 LSB
−0.01 ±0.005 +0.01 −0.01 ±0.005 +0.01 −0.01 ±0.005
±1.0 ±1.0 ±1.0
±1.0 ±1.0 ±1.0
8.66 20.2
−1.0
10
1
31.66 8.66
+1.0 −1.0
20.2
10
1
31.66 8.66
1.0 −1.0
20.2
10
1
+0.01 % FSR
% FSR
% FSR
31.66
+1.0
mA
V
pF
0 0 0 ppm/°C
80 80 80 ppm/°C
40 40 40 ppm/°C
1.14 1.2
5
1.26 1.14 1.2
5
1.26 1.14 1.2
5
1.26 V
3.13 3.3
1.70 1.8
3.47 3.13 3.3
1.90 1.70 1.8
3.47 3.13 3.3
1.90 1.70 1.8
3.47 V
1.90 V
3.13 3.3
1.70 1.8
3.47 3.13 3.3
1.90 1.70 1.8
3.47 3.13 3.3
1.90 1.70 1.8
3.47 V
1.90 V
25 25 25 mA
47 47 47 mA
10 10 10 mA
122 122 122 mA
380 380 380 mW
25 25 25 mA
47 47 47 mA
10 10 10 mA
234 234 234 mA
550 550 550 mW
Rev. A | Page 4 of 72

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AD9734/AD9735/AD9736
Parameter
Static, No Clock
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
Sleep Mode, No Clock
IAVDD33
FIR Bypass (1×) Mode
Power-Down Mode3
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
AD9736
AD9735
AD9734
Min Typ
Max Min Typ
Max Min Typ
Max Unit
25 25 25 mA
8 8 8 mA
10 10 10 mA
2 2 2 mA
133 133 133 mW
2.5 3.15
59 65
2.5 3.15
59 65
2.5 3.15 mA
59 65 mW
0.01 0.13
0.02 0.12
0.01 0.12
0.01 0.11
0.12 1.24
0.01 0.13
0.02 0.12
0.01 0.12
0.01 0.11
0.12 1.24
0.01 0.13 mA
0.02 0.12 mA
0.01 0.12 mA
0.01 0.11 mA
0.12 1.24 mW
1 Default band gap adjustment (Reg. 0x0E <2:0> = 0x0).
2 Use an external amplifier to drive any external load.
3 Typical wake-up time is 8 μs with recommended 1 nF capacitor on VREF pin.
Rev. A | Page 5 of 72