AD9911.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AD9911 데이타시트 다운로드

No Preview Available !

Data Sheet
500 MSPS Direct Digital Synthesizer
with 10-Bit DAC
AD9911
FEATURES
Patented SpurKiller technology
Multitone generation
Test-tone modulation
Up to 800 Mbps data throughput
Matched latencies for frequency/phase/amplitude changes
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of FSK, PSK, ASK
Programmable DAC full-scale current
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude-scaling resolution
Software-/hardware-controlled power-down
Multiple device synchronization
Selectable 4× to 20× REF_CLK multiplier (PLL)
Selectable REF_CLK crystal oscillator
56-lead LFCSP
APPLICATIONS
Agile local oscillator
Test and measurement equipment
Commercial and amateur radio exciter
Radar and sonar
Test-tone generation
Fast frequency hopping
Clock generation
GENERAL DESCRIPTION
The AD9911 is a complete direct digital synthesizer (DDS).
This device includes a high speed DAC with excellent wideband
and narrowband spurious-free dynamic range (SFDR) as well as
three auxiliary DDS cores without assigned digital-to-analog
converters (DACs). These auxiliary channels are used for spur
reduction, multitone generation, or test-tone modulation.
The AD9911 is the first DDS to incorporate SpurKiller
technology and multitone generation capability. Multitone
mode enables the generation up to four concurrent carriers;
frequency, phase and amplitude can be independently
programmed. Multitone generation can be used for system
tests, such as inter-modulation distortion and receiver blocker
sensitivity. SpurKilling enables customers to improve SFDR
performance by reducing the magnitude of harmonic
components and/or the aliases of those harmonic components.
Test-tone modulation efficiently enables sine wave modulation
of amplitude on the output signal using one of the auxiliary
DDS cores.
The AD9911 can perform modulation of frequency, phase, or
amplitude (FSK, PSK, ASK). Modulation is implemented by
storing profiles in the register bank and applying data to the
profile pins. In addition, the AD9911 supports linear sweep of
frequency, phase, or amplitude for applications such as radar
and instrumentation.
(continued on Page 3)
500MSPS
DDS CORE
10-BIT DAC
SYSTEM
CLOCK
SOURCE
SPUR REDUCTION/
MODULATION CONTROL
MULTITONE
REF CLOCK
INPUT CIRCUITRY
TIMING AND
CONTROL
RECONSTRUCTED
SINE WAVE
USER INTERFACE
Figure 1. Basic Block Diagram
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

No Preview Available !

AD9911
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Equivalent Input and Output Circuits....................................... 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Application Circuits ....................................................................... 17
Theory of Operation ...................................................................... 18
Primary DDS Core ..................................................................... 18
SpurKiller/Multitone Mode and Test-Tone Modulation....... 18
D/A Converter ............................................................................ 18
Modes of Operation ....................................................................... 19
Single-Tone Mode ...................................................................... 19
SpurKiller/Multitone Mode ...................................................... 19
Test-tone Mode ........................................................................... 20
Reference Clock Modes ............................................................. 20
Scalable DAC Reference Current Control Mode ................... 21
Power-Down Functions............................................................. 21
Shift Keying Modulation ........................................................... 21
Shift Keying Modulation Using SDIO Pins for RU/RD ........ 23
Linear Sweep (Shaped) Modulation Mode ............................. 23
REVISION HISTORY
11/2016—Rev. 0 to Rev. A
Changes to Figure 43 Caption....................................................... 25
Updated Outline Dimensions ....................................................... 41
5/2006—Revision 0: Initial Version
Data Sheet
Linear Sweep No Dwell Mode .................................................. 25
Sweep and Phase Accumulator Clearing Functions .............. 26
Output Amplitude Control ....................................................... 26
Synchronizing Multiple AD9911 Devices................................... 28
Operation .................................................................................... 28
Automatic Mode Synchronization ........................................... 28
Manual Software Mode Synchronization................................ 28
Manual Hardware Mode Synchronization.............................. 28
I/O_Update, SYNC_CLK, and System Clock Relationships 29
I/O Port............................................................................................ 30
Overview ..................................................................................... 30
Instruction Byte Description .................................................... 30
I/O Port Pin Description........................................................... 31
I/O Port Function Description ................................................. 31
MSB/LSB Transfer Description ................................................ 31
I/O Modes of Operation............................................................ 31
Register Maps.................................................................................. 35
Control Register Map ................................................................ 35
Channel Register Map ............................................................... 36
Profile Register Map................................................................... 37
Control Register Descriptions ...................................................... 38
Channel Select Register (CSR) ................................................. 38
Channel Function Register (CFR) Description...................... 39
Outline Dimensions ....................................................................... 41
Ordering Guide .......................................................................... 41
Rev. A | Page 2 of 41

No Preview Available !

Data Sheet
GENERAL DESCRIPTION
The DDS acts as a high resolution frequency divider with the
REF_CLK as the input and the DAC providing the output. The
REF_CLK input can be driven directly or used in combination
with an integrated REF_CLK multiplier (PLL). The REF_CLK
input also features an oscillator circuit to support an external
crystal as the REF_CLK source. The crystal can be used in
combination with the REF_CLK multiplier.
The AD9911 I/O port offers multiple configurations to provide
significant flexibility. The I/O port offers an SPI-compatible
mode of operation that is virtually identical to the SPI operation
found in earlier Analog Devices DDS products.
AD9911
Flexibility is provided by four data pins (Pin SDIO_0,
Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow four
programmable modes of I/O operation.
The DAC output is supply referenced and must be terminated
into AVDD by a resistor and an AVDD center-tapped trans-
former. The DAC has its own programmable reference to enable
different full-scale currents.
The DDS core (the AVDD pins and the DVDD pins) is powered
by a 1.8 V supply. The digital I/O interface (SPI) operates at
3.3 V and requires that the Pin DVDD_I/O (Pin 49) be
connected to 3.3 V.
AD9911
32 Σ
32
FTW/ 32
FTW
FUNCTIONAL BLOCK DIAGRAM
Σ Σ 15 COS(X) 10 10 Σ
DAC
PHASE/
PHASE
14
AMP/
AMP
10
SCALABLE
DAC REF
CURRENT
SPURKILLER/
MULTI-TONE
DDS
CORE
MUX
DDS
DDS
CORE CORE
SYNC_IN
SYNC_OUT
I/O_UPDATE
SYNC_CLK
REF_CLK
REF_CLK
TIMING AND CONTROL LOGIC
÷4
BUFFER/
XTAL
OSCILLATOR
REF CLOCK
MULTIPLIER
4× TO 20×
SYSTEM
CLK
MUX
1.8V
1.8V
CONTROL
REGISTERS
CHANNE L
REGISTERS
PROFILE
REGISTERS
CLK_MODE_SEL
LOOP FILTER
AVDD DVDD
P0 P1 P2 P3
Figure 2. Functional Block Diagram
I/O
PORT
BUFFER
3.3V
DVDD_I/O
IOUT
IOUT
DAC_RSET
PWR_DWN_CTL
MASTER_RESET
SCLK
CS
SDIO_0
SDIO_1
SDIO_2
SDIO_3
Rev. A | Page 3 of 41

No Preview Available !

AD9911
Data Sheet
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK
multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier Bypassed
REF_CLK Multiplier Enabled
Internal VCO Output Frequency Range
VCO Gain Bit Set1
Internal VCO Output Frequency Range
VCO Gain Bit Cleared
Crystal REF_CLK Source Range
Input Power Sensitivity
Input Voltage Bias Level
Input Capacitance
Input Impedance
Duty Cycle with REF_CLK Multiplier Bypassed
Duty Cycle with REF_CLK Multiplier Enabled
CLK Mode Select (Pin 24) Logic 1 V
CLK Mode Select (Pin 24) Logic 0 V
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
Output Current Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Voltage Compliance Range
WIDEBAND SFDR
Min
1
10
255
100
20
5
45
35
1.25
10
AVDD –
0.50
1 MHz to 20 MHz Analog Output
20 MHz to 60 MHz Analog Output
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 t MHz to 200 MHz Analog Output
WIDEBAND SFDR Improvement
Spur Reduction Enabled
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 MHz to 200 MHz Analog Output
Typ Max
500
125
500
160
1.15
2
1500
30
+3
55
65
1.8
0.5
10
+10
1 25
±0.5
±1.0
3
AVDD +
0.50
65
62
59
56
53
8
15
12
Unit
MHz
MHz
MHz
MHz
MHz
dBm
V
pF
%
%
V
V
mA
%FS
µA
LSB
LSB
pF
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Test Conditions/Comments
Measured at the pin (single-ended)
1.8 V digital input logic
1.8 V digital input logic
Must be referenced to AVDD
10 mA is set by RSET = 1.91 kΩ
The frequency range for wideband SFDR is
defined as dc to Nyquist
Programs devices on an individual basis to
enable spur reduction. See the
SpurKiller/Multitone Mode section.
Rev. A | Page 4 of 41

No Preview Available !

Data Sheet
AD9911
Parameter
Min Typ Max Unit Test Conditions/Comments
NARROWBAND SFDR
1.1 MHz Analog Output (±10 kHz)
90 dBc
1.1 MHz Analog Output (±50 kHz)
88 dBc
1.1 MHz Analog Output (±250 kHz)
86 dBc
1.1 MHz Analog Output (±1 MHz)
85 dBc
15.1 MHz Analog Output (±10 kHz)
90 dBc
15.1 MHz Analog Output (±50 kHz)
87 dBc
15.1 MHz Analog Output (±250 kHz)
85 dBc
15.1 MHz Analog Output (±1 MHz)
83 dBc
40.1 MHz Analog Output (±10 kHz)
90 dBc
40.1 MHz Analog Output (±50 kHz)
87 dBc
40.1 MHz Analog Output (±250 kHz)
84 dBc
40.1 MHz Analog Output (±1 MHz)
82 dBc
75.1 MHz Analog Output (±10 kHz)
87 dBc
75.1 MHz Analog Output (±50 kHz)
85 dBc
75.1 MHz Analog Output (±250 kHz)
83 dBc
75.1 MHz Analog Output (±1 MHz)
82 dBc
100.3 MHz Analog Output (±10 kHz)
87 dBc
100.3 MHz Analog Output (±50 kHz)
85 dBc
100.3 MHz Analog Output (±250 kHz)
83 dBc
100.3 MHz Analog Output (±1 MHz)
81 dBc
200.3 MHz Analog Output (±10 kHz)
87 dBc
200.3 MHz Analog Output (±50 kHz)
85 dBc
200.3 MHz Analog Output (±250 kHz)
83 dBc
200.3 MHz Analog Output (±1 MHz)
81 dBc
PHASE NOISE CHARACTERISTICS
Residual Phase Noise @ 15.1 MHz (fOUT)
1 kHz Offset
–150
dBc/Hz
10 kHz Offset
–159
dBc/Hz
100 kHz Offset
–165
dBc/Hz
1 MHz Offset
–165
dBc/Hz
Residual Phase Noise @ 40.1 MHz (fOUT)
1 kHz Offset
–142
dBc/Hz
10 kHz Offset
–151
dBc/Hz
100 kHz Offset
–160
dBc/Hz
1 MHz Offset
–162
dBc/Hz
Residual Phase Noise @ 75.1 MHz (fOUT)
1 kHz Offset
–135
dBc/Hz
10 kHz Offset
–146
dBc/Hz
100 kHz Offset
–154
dBc/Hz
1 MHz Offset
–157
dBc/Hz
Residual Phase Noise @ 100.3 MHz (fOUT)
1 kHz Offset
–134
dBc/Hz
10 kHz Offset
–144
dBc/Hz
100 kHz Offset
–152
dBc/Hz
1 MHz Offset
–154
dBc/Hz
Rev. A | Page 5 of 41