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Data Sheet
February 10, 2006
ISL6315
FN9222.0
Two-Phase Multiphase Buck PWM
Controller with Integrated MOSFET
Drivers
The ISL6315 two-phase PWM control IC provides a
precision voltage regulation system for advanced loads up to
60A-80A. Multiphase power conversion is a marked
departure from single phase converter configurations
employed to satisfy the increasing current demands of
modern microprocessors and other electronic circuits. By
distributing the power and load current, implementation of
multiphase converters utilize smaller and lower cost
transistors with fewer input and output capacitors. These
reductions accrue from the higher effective conversion
frequency with higher frequency ripple current due to the
phase interleaving process of this topology.
Outstanding features of this controller IC include programmable
VID codes compatible with Intel VRM9, VRM10, as well as
AMD’s Hammer microprocessors, along with a system
regulation accuracy of ±1%. The ISL6315, though, does not
intrinsically allow for load-line regulation (no droop).
Important features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the microprocessor. Like other Intersil multiphase
controllers, the ISL6315 uses cost and space-saving
rDS(ON) sensing for channel current balance and
overcurrent protection. Channel current balancing is
automatic and accurate with the integrated current-balance
control system. Overcurrent protection can be tailored to any
application with no need for additional parts. These features
provide intelligent protection for modern power systems.
Ordering Information
PART
NUMBER
PART TEMP.
MARKING (°C)
PACKAGE
PKG.
DWG. #
ISL6315CR ISL6315CR 0 to 70 24 Ld 4x4 QFN L24.4x4B
ISL6315CRZ 6315CRZ
(Note)
0 to 70 24 Ld 4x4 QFN L24.4x4B
(Pb-free)
ISL6315IRZ
(Note)
6315IRZ
-40 to 85 24 Ld 4x4 QFN L24.4x4B
(Pb-free)
ISL6315EVAL1
Evaluation Platform
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
**Contact Factory for Availability.
Features
• Integrated Two-Phase Power Conversion
• 5V to 12V Input Voltage Conversion
• Precision Channel Current Sharing
- Loss-Less Current Sampling - Uses rDS(ON)
• Precision Output Voltage Regulation
- ±1% System Accuracy Over Temperature (Commercial)
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD’s
Hammer DAC codes
• Fast Transient Recovery Time
• Overcurrent Protection
• Pre-Biased Output Start-up Operation
• Sources and Sinks Output Current
- Bus Termination Applications
• Improved, Multi-tiered Overvoltage Protection
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6315 (QFN)
TOP VIEW
24 23 22 21 20 19
VID1 1
18 PHASE1
VID0 2
17 LGATE1
DACSEL/VID5 3
VRM10 4
25
GND
16 PVCC
15 LGATE2
COMP 5
14 PGND
FB 6
13 PHASE2
7 8 9 10 11 12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
1.65V/1.95V +
-
COMP
VID0
VID1
VID2
VID3
VID4
DACSEL/VID5
VRM10
+
200mV
-
TTL D/A
CONVERTER
(VID DAC)
OVP WHILE
DISABLED
OVP
EA
+
-
OC
FB
GND
OFFSET
SOURCE
Σ
2
SSEND
ENLL VCC PVCC
OSCILLATOR
POWER-ON
RESET (POR)
GATE
CONTROL
SOFT-START
AND
FAULT LOGIC
Σ
Σ
CURRENT
CORRECTION
PWM1
PWM2
CONTROL
LOGIC
GATE
CONTROL
OFS
ISEN
BOOT1
UGATE1
PHASE1
LGATE1
PGND
BOOT2
UGATE2
PHASE2
LGATE2

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Simplified Power System Diagram
+5VIN
ISL6315
5-6
VID
DAC
CHANNEL1
ISL6315
CHANNEL2
Q1
Q2
Q3
Q4
VOUT
Typical Application
+12VIN
+5VIN
CF1
DACSEL/VID12
VID4
VID3
VID2
VID1
VID0
VRM10
RISEN
ISEN
R’OFS
ROFS
SSEND
ENLL
OFS
VCC
LIN
CF2
CHFIN1
PVCC
BOOT1
UGATE1
CBOOT1
Q1
PHASE1
CBIN1
LOUT1
ISL6315
LGATE1
Q2
BOOT2
UGATE2
CBOOT2
CHFIN2
Q3
CBIN2
COMP
C2
C1
R2
FB
R1
PHASE2
LGATE2
PGND
GND
LOUT2
Q4
CHFOUT
VOUT
CBOUT
3 FN9222.0
February 10, 2006

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ISL6315
Absolute Maximum Ratings
Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . -0.3V to +6.25V
Absolute Boot Voltage, VBOOT . . . . . PGND - 0.3V to PGND + 27V
Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V
Lower Gate Voltage, VLGATE. . . . . . . . PGND - 0.3V to VCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . HBM Class 1 JEDEC STD
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
45
7.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VCC = 5V, TJ = 0°C to 85°C, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
VCC POR (Power-On Reset) Threshold
IVCC; ENLL = high
VCC Rising
-
4.2
VCC Falling
3.7
PVCC POR (Power-On Reset) Threshold
PVCC Rising
-
PVCC Falling
-
Switching Frequency (per channel)
Oscillator Ramp Amplitude
Maximum Duty Cycle (Note 3)
TJ = 25°C to 85°C
TJ = -40°C
VP-P
189
166
-
-
CONTROL THRESHOLDS
ENLL Rising Threshold
-
ENLL Falling Threshold
-
REFERENCE AND DAC
System Accuracy
-1
DAC Input Low Voltage
TJ = -40°C to 85°C
-1.5
-
DAC Input High Voltage
0.8
DAC Input Pull-Up Current
VIDx = 0V
-
ERROR AMPLIFIER
DC Gain (Note 3)
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
Maximum Output Voltage
RL = 10K to ground
CL = 100pF, RL = 10K to ground
CL = 100pF, Load = ±400µA
Load = 1mA
-
-
-
3.90
Minimum Output Voltage
Load = -1mA
-
OVERCURRENT PROTECTION
Overcurrent Trip Level
72
TYP
4
4.4
3.9
4.3
3.3
222
205
1.33
67
0.645
0.567
-
-
-
-
45
96
20
8
4.20
0.80
95
MAX UNITS
6 mA
4.6 V
4.1 V
-V
-V
255 kHz
241 kHz
-V
-%
-V
- mV
1%
1.5 %
0.4 V
-V
- µA
- dB
- MHz
- V/µs
-V
0.90 V
115 µA
4 FN9222.0
February 10, 2006

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ISL6315
Electrical Specifications Test Conditions: VCC = 5V, TJ = 0°C to 85°C, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP
PROTECTION
Overvoltage Threshold while IC Disabled
VRM9.0 configuration
1.90 1.95
Hammer and VRM10.0 configurations
1.60 1.65
Overvoltage Threshold
FB Rising
- VID
+200mV
Overvoltage Hysteresis
- 100
SWITCHING TIME
UGATE Rise Time (Note 3)
LGATE Rise Time (Note 3)
UGATE Fall Time (Note 3)
LGATE Fall Time (Note 3)
UGATE Turn-On Non-overlap (Note 3)
LGATE Turn-On Non-overlap (Note 3)
OUTPUT
tRUGATE; VVCC = 5V, 3nF Load
tRLGATE; VVCC = 5V, 3nF Load
tFUGATE; VVCC = 5V, 3nF Load
tFLGATE; VVCC = 5V, 3nF Load
tPDHUGATE; VVCC = 5V, 3nF Load
tPDHLGATE; VVCC = 5V, 3nF Load
-8
-8
-8
-4
-8
-8
Upper Drive Source Resistance
100mA Source Current
- 1.0
Upper Drive Sink Resistance
100mA Sink Current
- 1.0
Lower Drive Source Resistance
100mA Source Current
- 1.0
Lower Drive Sink Resistance
100mA Sink Current
- 0.4
NOTES:
3. Parameter magnitude guaranteed by design.
MAX UNITS
2.00 V
1.70 V
-V
- mV
- ns
- ns
- ns
- ns
- ns
- ns
2.5
2.5
2.5
1.0
Timing Diagram
tPDHUGATE
tRUGATE
tFUGATE
UGATE
LGATE
tFLGATE
tPDHLGATE
tRLGATE
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1µF
ceramic capacitor.
PVCC (Pin 16)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1µF
ceramic capacitor.
5
GND and PGND (Pins 25 and 14)
Connect these pins to the circuit ground using the shortest
possible paths. All internal small-signal circuitry is
referenced to the GND pin. LGATE drive is referenced to the
PGND pin.
VID0-4 (Pins 2, 1, 24-22)
Voltage identification inputs from microprocessor. These pins
respond to TTL logic thresholds. The ISL6315 decodes the
VID inputs to establish the output voltage; see VID Tables for
correspondence between DAC codes and output voltage
settings. These pins are internally pulled high, to
approximately 1.2V, by 40µA (typically) internal current
FN9222.0
February 10, 2006