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Data Sheet
16-Bit, 250 kSPS, Unipolar/Bipolar
Programmable Input PulSAR® ADC
AD7610
FEATURES
Multiple pins/software programmable input ranges:
5 V, 10 V, ±5 V, ±10 V
Pins or serial SPI®-compatible input ranges/mode selection
Throughput: 250 kSPS
16-bit resolution with no missing codes
INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
SNR: 94 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C;
On-chip temperature sensor
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation
90 mW @ 250 kSPS
10 mW @ 1 kSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND
AGND
AVDD
PDREF
PDBUF
IN+
IN–
REF
AMP
REF
SWITCHED
CAP DAC
CNVST
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
AD7610
SERIAL
DATAPORT
SERIAL
CONFIGURATION
PORT
16
PARALLEL
INTERFACE
OVDD
OGND
D[15:0]
SER/PAR
BYTESWAP
OB/2C
BUSY
RD
CS
BIPOLAR TEN
Figure 1.
GENERAL DESCRIPTION
The AD7610 is a 16-bit charge redistribution successive approxi-
mation register (SAR), architecture analog-to-digital converter
(ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage
process. The device is configured through hardware or via a
dedicated write only serial configuration port for input range
and operating mode. The AD7610 contains a high speed 16-bit
sampling ADC, an internal conversion clock, an internal reference
(and buffer), error correction circuits, and both serial and parallel
system interface ports. A falling edge on CNVST samples the
analog input on IN+ with respect to a ground sense, IN−. The
AD7610 features four different analog input ranges: 0 V to 5 V, 0 V
to 10 V, ±5 V, and ±10 V. Power consumption is scaled linearly
with throughput. The device is available in Pb-free 48-lead, low-
profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from −40°C to
+85°C.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
Type
100 kSPS to 500 kSPS to 800 kSPS to
250 kSPS
570 kSPS
1000 kSPS
Pseudo
Differential
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
True Bipolar
AD7610
AD7663
AD7665
AD7612
AD7671
AD7951
True
Differential
AD7675
AD7676
AD7677
18-Bit, True
Differential
Multichannel/
Simultaneous
AD7678
AD7679
AD7654
AD7655
AD7674
>1000
kSPS
AD7621
AD7622
AD7623
AD7641
AD7643
Rev. A
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AD7610
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Overview...................................................................................... 16
Converter Operation.................................................................. 16
Transfer Functions...................................................................... 17
Typical Connection Diagram ................................................... 18
Analog Inputs.............................................................................. 19
REVISION HISTORY
12/12—Rev. 0 to Rev. A
Added Exposed Pad Note................................................................ 8
Changes to Power Sequencing Section........................................ 23
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
10/06—Revision 0: Initial Version
Data Sheet
Voltage Reference Input/Output .............................................. 20
Power Supplies ............................................................................ 21
Conversion Control ................................................................... 22
Interfaces.......................................................................................... 23
Digital Interface.......................................................................... 23
Parallel Interface......................................................................... 23
Serial Interface ............................................................................ 24
Master Serial Interface............................................................... 24
Slave Serial Interface .................................................................. 26
Hardware Configuration ........................................................... 28
Software Configuration ............................................................. 28
Microprocessor Interfacing....................................................... 29
Application Information................................................................ 30
Layout Guidelines....................................................................... 30
Evaluating Performance ............................................................ 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Rev. A | Page 2 of 32

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Data Sheet
AD7610
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range, VIN
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error2
No Missing Codes2
Differential Linearity Error2
Transition Noise
Zero Error (Unipolar or Bipolar)
Zero Error Temperature Drift
Bipolar Full-Scale Error
Unipolar Full-Scale Error
Full-Scale Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Dynamic Range
Signal-to-Noise Ratio
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion
Spurious-Free Dynamic Range
–3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
Transient Response
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Long-Term Drift
Turn-On Settling Time
REFERENCE BUFFER
REFBUFIN Input Voltage Range
Conditions/Comments
VIN+ − VIN− = 0 V to 5 V
VIN+ − VIN− = 0 V to 10 V
VIN+ − VIN− = ±5 V
VIN+ − VIN− = ±10 V
VIN− to AGND
fIN = 100 kHz
VIN = ±5 V, ±10 V @ 250 kSPS
See Analog Inputs section
AVDD = 5 V ± 5%
VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB
VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB
VIN = ±10 V, fIN = 2 kHz, −60 dB
VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz
VIN = ±5 V, ±10 V, fIN = 2 kHz
VIN = 0 V to 5 V, fIN = 20 kHz
VIN = ±5 V, fIN = 2 kHz
VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz
VIN = ±10 V, fIN = 2 kHz
fIN = 2 kHz
fIN = 2 kHz
VIN = 0 V to 5 V
Full-scale step
PDREF = PDBUF = low
REF @ 25°C
–40°C to +85°C
AVDD = 5 V ± 5%
1000 hours
CREF = 22 µF
PDREF = high
Min
16
−0.1
−0.1
−5.1
−10.1
−0.1
−1.5
16
−1
−35
−50
−70
92.5
92
4.965
2.4
Typ Max
+5.1
+10.1
+5.1
+10.1
+0.1
75
1001
4
250
±0.75 +1.5
+1.5
0.55
+35
±1
+50
+70
±1
3
93.5
94
94.5
93
94
93.5
92.5
93
93.5
−107
107
650
2
5
500
5.000
±3
±15
50
10
5.035
2.5 2.6
Unit
Bits
V
V
V
V
V
dB
µA
μs
kSPS
LSB3
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
LSB
dB4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
kHz
ns
ps rms
ns
V
ppm/°C
ppm/V
ppm
ms
V
Rev. A | Page 3 of 32

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AD7610
Data Sheet
Parameter
EXTERNAL REFERENCE
Voltage Range
Current Drain
TEMPERATURE PIN
Voltage Output
Temperature Sensitivity
Output Resistance
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay5
VOL
VOH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
VCC
VEE
Operating Current7, 8
AVDD
With Internal Reference
With Internal Reference Disabled
DVDD
OVDD
VCC
VEE
Power Dissipation
With Internal Reference
With Internal Reference Disabled
In Power-Down Mode9
TEMPERATURE RANGE10
Specified Performance
Conditions/Comments
PDREF = PDBUF = high
REF
250 kSPS throughput
@ 25°C
Parallel or serial 16-bit
ISINK = 500 µA
ISOURCE = –500 µA
@ 250 kSPS throughput
VCC = 15 V, with internal reference buffer
VCC = 15 V
VEE = −15 V
@ 250 kSPS throughput
PDREF = PDBUF = low
PDREF = PDBUF = high
PD = high
TMIN to TMAX
Min
Typ Max
Unit
4.75 5 AVDD + 0.1 V
30 µA
311 mV
1 mV/°C
4.33 kΩ
−0.3 +0.6 V
2.1 OVDD + 0.3 V
−1 +1 µA
−1 +1 µA
OVDD − 0.6
0.4
4.756
4.75
2.7
7
−15.75
5 5.25
5 5.25
5.25
15 15.75
−15 0
8
6.3
3.3
0.3
1.4
0.8
0.7
90 110
70 90
10
−40 +85
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mW
mW
µW
°C
1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 40 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5 Conversion results are available immediately after completed conversion.
6 4.75 V or VREF – 0.1 V, whichever is larger.
7 Tested in parallel reading mode.
8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9 With all digital inputs forced to OVDD.
10 Consult sales for extended temperature range.
Rev. A | Page 4 of 32

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Data Sheet
AD7610
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES1 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay1
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period2
Internal SDCLK High2
Internal SDCLK Low2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SDCLK Last Edge to SYNC Delay2
CS High to SYNC HI-Z
CS High to Internal SDCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert2
CNVST Low to SYNC Delay, Read After Convert
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1 (See Figure 42,
Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
Min
10
4
10
380
10
20
2
3
30
15
10
4
5
5
5
2
5
5
25
10
10
Typ Max
35
1.45
2
1.45
1.41
40
15
10
10
10
560
45
See Table 4
1.31
25
10
10
10
18
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
1 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial mode read after convert mode.
Rev. A | Page 5 of 32