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U2733B-C
Fractional-N Frequency Synthesizer for DAB Tuner
Description
The U2733B-C is a monolithically integrated
fractional-N frequency synthesizer circuit fabricated in
TEMIC’s advanced UHF5S technology. Designed for
applications in DAB receivers, it controls a VCO to
synthesize frequencies in the range of 70 to 500 MHz in
a 16 kHz raster; four different reference divide factors can
be selected. The lock status of the phase detector is
indicated at a special output pin, six switching outputs can
be addressed. An internal frequency doubler provides an
output signal having twice the frequency of the reference
oscillator. All functions of this IC are controlled by
I2C bus.
Features
D Microprocessor controlled via I2C bus
D 4 addresses selectable
D Four reference divide factors selectable:
1024, 1120, 1152, 1536
D Effectively
D Programmable 15-bit counter 1:2048 to 1:32767
effectively
D Three state phase detector with programmable charge
pump
D Superior phase noise performance
D Deactivation of tuning output programmable
D 6 switching outputs (open collector)
D Reference frequency doubler (open collector output)
D Lock status indication (open collector)
D Fully compatible to U2753B-C
D SSO20 package
Block Diagram
REF
NREF
4
5
RF
NRF
18
17
Frequency doubler
x2
FDO NFDO
10 9
Reference counter
Fractional N
control
Prog.
13 Bit counter
N/N=1
Three State
Phase
Detector
Lock detector
Prog.
charge pump
4 Bit latch
3
PLCK
1
PD
2
VD
7 Bit latch
2 Bit
latch
5 Bit latch
I2C Bus –Interface / Control
MUX
MUX
Switches
19 20
GND VS
67
8 11 12 13 14 15 16
ADR
SCL
SDA
SWC SWD SWE SWF SWG SWH
12476
Figure 1. Block diagram
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
Preliminary Information
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U2733B-C
Pin Description
PD
VD
PLCK
REF
NREF
ADR
SCL
1
2
3
4
5
6
7
20 VS
19 GND
18 RF
17 NRF
16 SWH
15 SWG
14 SWF
SDA
8
13 SWE
NFDO
FDO
9 12 SWD
10 11 SWC
12484
Figure 2. Pinning
Pin Symbol
Function
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 PD Three-state charge pump output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2 VD Active filter output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ3 PLCK Lock indicating output
(open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ4 REF Reference input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ5 NREF Reference input (inverted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ6 ADR Address selection
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ7 SCL Clock (I2C)
8 SDA Data (I2C)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ9 NFDO Frequency doubler output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(inverted, open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ10 FDO Frequency doubler output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ11 SWC Switching output
(opencollector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ12 SWD Switching output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ13 SWE Switching output
(open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ14 SWF Switching output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ15 SWG Switching output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(open collector)
16 SWH Switching output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(open collector)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ17 NRF RF input (inverted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ18 RF RF input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ19 GND Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ20 VS Supply voltage
Functional Description
The U2733B-C is a low power fractional-N frequency
synthesizer designed for applications in DAB receivers.
Its RF operation range reaches from 70 MHz up to
500 MHz. The device includes input buffers for reference
and RF dividers, a reference divider, a programmable RF
divider using fractional-N technique, a tri-state phase
detector, a programmable charge pump, six switching
outputs, a frequency doubler for the reference input signal
and a control unit. The control unit has to be accessed by
a micro controller via I2C bus. The programming
information is stored in a set of internal registers.
The basic difference of this circuit from the U2753B-C is
the use of a special phase noise shaping technique based
on the fractional-N principle which concentrates the
phase detector’s phase noise contribution to the spectrum
of the controlled VCO at frequency positions where it
doesn’t damage the quality of the received DAB signal.
In critical locations of the VCO’s frequency spectrum the
phase detectors phase noise contribution is reduced by
roughly 12 dB. A special property of the transmission
technique which is used in DAB is that the phase noise
weighting function which measures the influence of the
LO’s phase noise to the phase information of the coded
signal in a DAB receiver has zeros, i.e., if phase noise is
concentrated in the position of such zeros as discrete lines
the DAB signal is not disturbed as long as these lines don’t
exceed a certain limit.
2 (14)
TELEFUNKEN Semiconductors
Preliminary Information
Rev. A1, 21-Aug-96

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U2733B-C
For DAB mode I this phase noise weighting function is
shown in the following figure:
1,80
1,60
1,40
1,20
1,00
0,80
0,60
0,40
0,20
0,00
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
df / Hz
12477
Figure 3.
It is important to realize that this function shows zeros in
all distances from the center line which are multiples of
the carrier spacing. The technique of concentrating the
phase noise in the positions of such zeros is protected by
a patent.
In this circuit the phase detector is operated at a frequency
which is four times the desired frequency raster spacing
(e.g., 16 kHz in case of DAB) and the well known
fractional-N technique is used to synthesize the raster. As
a result of this technique in the VCO’s frequency
spectrum spurious occur not only in multiples of the phase
detectors input comparison frequency (64 kHz) but also
in multiples of the raster frequency (16 kHz). As
described above for all DAB modes these spurious are
placed in spectral positions where the phase noise
weighting function is zero. Therefore no measures are
necessary to suppress these lines.
Reference Divider
Four different scaling factors SFref of the reference
divider can be selected by means of the bits ‘RD1’ and
‘RD2’ in the I2C bus instruction code: 256, 280, 288, and
384. Starting from a reference oscillator frequency of
16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz
these scaling factors provide a frequency raster of
64 kHz. By changing the division ratio of the main
divider from N to N+1 in an appropriate way
(fractional-N technique) this frequency raster is
interpolated to deliver a frequency spacing of 16 kHz
according to the DAB specification. So effectively the
reference divide factors 1024, 1120, 1152 and 1536 can
be selected. By setting of the I2C bus bit ‘T’ a test signal
representing the divided input signal can be monitored at
the switching output SWC.
Main Divider
The main divider consists of a fully programmable 13-bit
divider which defines a division ratio N. The applied
division ratio is either N or N+1 according to the control
of a special control unit. On average the scaling factors
SF = N+k/ 4 can be selected where k = 0, 1, 2, 3. In this
way VCO frequencies
fVCO = 4 (N+k/4) fref/(4 SFref)
can be synthesized starting from a reference frequency
fref.. If we define SFeff = 4 N+k and SFref, eff = 4 SFref
we end up with
fVCO = SFeff fref/SFref,eff,
where SFeff is defined by 15 bits. In the following this
circuit is described in terms of SFeff and SFref,eff. SFeff has
to be programmed via the I2C bus interface. An effective
scaling factor from 2048 up to 32767 can be selected. By
setting of the I2C bus bit ‘T’ a test signal representing the
divided input signal can be monitored at the switching
output SWF.
When the supply voltage is switched on both the reference
divider and the programmable divider are kept in
RESET state till a complete scaling factor is written onto
the chip. Changes in the setting of the programmable
divider become active when the corresponding I2C bus
transmission is completed. By an internal synchro-
nization procedure is ensured that such changes don’t
become active while the charge pump is sourcing or
sinking current at its output pin. This behavior allows a
smooth tuning of the output frequency without disturbing
the controlled VCO’s frequency spectrum.
Phase Comparator and Charge Pump
The tri-state phase detector causes the charge pump to
source or to sink current at the output pin PD depending
on the phase relation of its input signals which are
provided by the reference and the main divider
respectively. Four different values of this current can be
selected by means of the I2C bus bits ‘I50’ and ‘I100’. By
use of this option for example changes of the loop
characteristics due to the variation of the VCO gain as a
function of the tuning voltage can be reduced. The charge
pump current can be switched off using the I2C bus bit
‘TRI’. A change in the setting of the charge pump current
becomes active when the corresponding I2C bus
transmission is completed. As described for the setting of
the scaling factor of the programmable divider an internal
synchronization procedure ensures that such changes
don’t become active while the charge pump is sourcing or
sinking current at its output pin. This behavior allows a
change in the charge pump current without disturbing the
controlled VCO’s frequency spectrum.
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
Preliminary Information
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U2733B-C
A high gain amplifier (output pin: VD) which is
implemented in order to construct a loop filter as shown
in the application circuit can be switched off by means of
the I2C bus bit ‘OS’.
An internal lock detector checks if the phase difference of
the input signals of the phase detector is smaller than
approximately 250 ns in seven subsequent comparisons.
If phase lock is detected the open collector output pin
PLCK is set ‘H’ (logical value!). It should be noted that
the output current of this pin must be limited by external
circuitry as it is not limited internally. If the I2C bus bit
‘TRI’ is set ‘H’ the lock detector function is deactivated
and the logical value of the PLCK output is undefined.
Switching Outputs
Six switching outputs controlled by the I2C bus bits
‘SWC’, ‘SWD’, ‘SWE’, ‘SWF’, ‘SWG’, ‘SWH’ can be
used for any switching task on the front end board. The
currents of these outputs are not limited internally. They
have to be limited by external circuitry.
Frequency Doubler
An internal frequency doubler provides a signal at twice
the frequency of the reference signal appearing at the
input pins REF and NREF. If the I2C bus bit ‘OFD’ = ‘H’
the current of its open collector outputs FDO and NFDO
is doubled. By means of the I2C bus bit ‘OFD’ the
frequency doubler function can be switched off.
As shown on page 15 (Integration in TEMIC DAB
Receiver Concept) the output signal of the frequency
doubler can be used in order to construct the LO signal of
the IF circuit (U2759B).
I2C Bus Interface
Via its I2C bus interface various functions can be
controlled by a microprocessor. These functions are
overviewed in the following sections ‘I2C bus instruction
codes’ and ‘I2C bus functions’. By means of the ADR pin
four different I2C bus addresses can be selected as
described in the section ‘Electrical characteristics’.
4 (14)
TELEFUNKEN Semiconductors
Preliminary Information
Rev. A1, 21-Aug-96

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U2733B-C
I2C Bus Instruction Codes
ÁÁÁÁÁÁÁADDDCCCÁÁÁÁÁÁÁooodiiivvvnnndiiitttrdddÁÁÁÁÁÁÁrrreeeeooosDrrrlllsebbbbbbÁÁÁÁÁÁÁbsyyyyyyyctttttttreeeeeeeiÁÁÁÁÁÁÁp123123tioÁÁÁÁÁÁÁn ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMOXXXF101SÁÁÁÁÁÁÁDB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2RIXXXD10FÁÁÁÁÁÁÁD1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSRnWnD00015ÁÁÁÁÁÁÁ1C2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSnOWnX0014S0ÁÁÁÁÁÁÁD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSWnnXT0093ÁÁÁÁÁÁÁE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSATnWnn0RS1824ÁÁÁÁÁÁÁ1IF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSIAn1Wnn0S107132GÁÁÁÁÁÁÁ0 ÁÁÁÁÁÁÁSÁÁÁÁÁÁÁLInWnn5S001600B2HÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I2C Bus Functions
I2C Bus Data Transfer
AS1, AS2 define the I2C bus address
Format
RD1, RD2 define the effective scaling factor of the
reference divider:
START – ADR – ACK – <instruction set> – STOP
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁRD1
RD2
Effective
The <instruction set> consists of a sequence of divider
Scaling
bytes and control bytes each followed by ACK. Divider
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFactor
byte i must be followed by divider byte i+1 (control byte
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 0 1120 1 if i = 3) or the instruction set must be finished. Control
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 0 1152 bytes have to be handled accordingly.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 1 1024
1
1
1536
Examples
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁni effective scaling factor (SFeff) of the main START–ADR–ACK–DB1–ACK–DB2–ACK–DB3
divider
SFeff = SUM(ni 2i)
– ACK – CB1 – ACK – CB2 –ACK – CB3 – ACK – STOP
OS OS = ‘H’ switches off tuning output
START – ADR – ACK – CB1 – ACK – CB2 – ACK –
T for T = ‘H’ reference signals describing the STOP
output frequencies of reference reference divider
and programmable divider are monitored at SWF However
(prog. div.) and SWC (ref. div.)
TRI TRI = ‘H’ switches off charge pump
I50, I100 define the charge pump current:
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁI50 I100 Charge Pumup Current
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(nominal)/A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’L’ ’L’
50
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’H’ ’L’
102
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’L’ ’H’
151
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’H’ ’H’
203
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁOFD OFD = ‘H’ switches off frequency doubler
START – ADR – ACK – DB1 – ACK – CB1 –ACK –
STOP
is not allowed.
Description
START
start condition
STOP
stop condition
ACK
acknoledge
ADR
address byte
2IFD
2IFD = ‘H’ doubles the frequency doubler output
current
DBi
divider byte i (i = 1, 2, 3)
SWa SWa = ‘H’ switches on output current
CBi control byte i (i = 1, 2, 3)
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
Preliminary Information
5 (14)