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Preliminary Data Sheet
INDT/R166B
INDT/R331B
Order this document by Q_DS_IND166-331
Long Distance Digital Display
Link Transmitter & Receiver
The GigaSTaRDigital Display Link 166/331-series is an
innovative high-speed link featuring simultaneous
transmission of digital video, audio and bi-directional
sideband data over one standard shielded twisted pair
cable up to 50 m (500 m with fiber optics). It supports
VGA…UXGA as well as Digital TV (DTV) and High-
Definition TV (HDTV) formats up to 720p or HDTV1080i
with up to 16.7 million colors. The sideband channels
provide bandwidth up to 264 Mbps to connect peripheral
components like keyboard, mouse, disc drive and audio
devices.
Compared to the 165/330-series the 166/331 offer
additional features like a tristate pixel interface (Rx only)
and an integrated pixel buffer to reducing pixel clock
variations. The 166/331 may be used as direct drop-in
replacement for the 165/330 under specified conditions.
INDT/R166B
INDT/R331B
INDT/R166B
INDT/R331B
VESA Format
at 18bit/60Hz
VGA…WXGA
VESA Format
at 24bit/60Hz
VGA…XGA
VGA…UXGA
VGA…SXGA
HDTV (24 bit)
480p (60fps), 720p (30fps)
480p (60fps), 720p (60fps), 1080i (30fps)
Features:
Parallel graphics controller and LC-display interfaces:
18- / 24-bit (1 pixel/clock)
36- / 48-bit (2 pixel/clock)
Pixel data clocking on rising/falling/both clock edges
Pixel Clock frequency: 24 – 161 MHz
Direct adaptation to DVI and LDI/LVDS standard interface
devices
4 channel audio interface (IEC958 compliant S/P-DIF)
High- and low-speed bi-directional sideband data channels
Single + 3.3 V power supply
Extended temperature range: -40 – +85 °C
Applications:
Long distance multimedia consoles
High resolution industrial remote terminals
Video broadcast systems
Long distance camera links
Machine vision systems
Digital TV equipment
Video Projectors and Home Cinemas
DVI Extension products
Typical Application:
PC
Graphics
C o n tro lle r
Camera
DVD
HDTV
VIDEO Transmitter
Receiver
DATA
AUDIO
INDT166B
or
INDT331B
STP-cable
INDR166B
or
INDR331B
VIDEO
TFT
LC-Display
DATA
AUDIO
Date: 2005-03-14 Revision: 0.1
Page 1 of 40

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Preliminary Data Sheet
INDT/R166B
INDT/R331B
Index
1 General Description ............................................................................................................................ 3
1.1 Link Interface ....................................................................................................................................3
1.1.1 Link Interface Bandwidth ............................................................................................................3
1.2 Pixel Interface ...................................................................................................................................4
1.2.1 General Information....................................................................................................................4
1.2.2 Pixel Interface Modes .................................................................................................................5
1.2.3 Pixel Clock Sampling Modes ......................................................................................................5
1.2.4 Pixel Data I/O Color Bit Mapping ................................................................................................7
1.3 Sideband Interface ............................................................................................................................8
1.3.1 General Information....................................................................................................................8
1.3.2 Low-speed Upstream Sideband Data Channel (SB0)..................................................................9
1.3.3 High-speed Upstream Sideband Data Channel (SB1).................................................................9
1.3.4 Low-speed Downstream Sideband Data Channel (SB2) .............................................................9
1.3.5 High-speed Downstream Sideband Data Channel (SB3, SB4). ...................................................9
1.3.6 Sideband Interface Signals.......................................................................................................10
1.4 Audio Interface................................................................................................................................11
2 Device Configuration ........................................................................................................................ 12
2.1 Pixel Clock Conditioning (Rx only) ...................................................................................................12
2.2 Configuration Vectors and Configuration Data .................................................................................13
2.3 Configuration Process and Timing ...................................................................................................14
2.4 Interface Configuration Scheme ......................................................................................................15
2.5 Error Handling and Reset ................................................................................................................15
3 Electrical Specification ..................................................................................................................... 16
3.1 External Circuits ..............................................................................................................................16
3.1.1 External Loop Filter Specification..............................................................................................16
3.1.2 Serial Transmission Cable Interconnect....................................................................................16
3.1.3 Serial Transmission Cable Termination.....................................................................................17
3.1.4 Receiver Equalizer ...................................................................................................................17
3.1.5 Reference Clock.......................................................................................................................17
3.1.6 VREF Reference Circuitry...........................................................................................................17
3.2 Power Supply..................................................................................................................................17
3.3 Absolute Maximum Ratings .............................................................................................................18
3.4 Recommended Operating Conditions ..............................................................................................18
3.5 AC–Characteristics (under recommended operating conditions, Reference Clock Freq. = 66 MHz)..19
3.6 DC–Characteristics (under recommended operating conditions) ......................................................19
3.7 Reference Clock Specification (Ta = -40 to 85° C; Vcc = 3.15 to 3.45 V)..........................................19
3.8 Timing Specification ........................................................................................................................20
4 Signals............................................................................................................................................... 27
4.1 INDT166B Transmitter Signal Description........................................................................................27
4.2 INDR166B Receiver Signal Description ...........................................................................................28
4.3 INDT331B Transmitter Signal Description........................................................................................30
4.4 INDR331B Receiver Signal Description ...........................................................................................32
5 Pin Assignment ................................................................................................................................. 34
5.1 INDT166B Transmitter ....................................................................................................................34
5.2 INDR166B Receiver ........................................................................................................................35
5.3 INDT331B Transmitter ....................................................................................................................36
5.4 INDR331B Receiver ........................................................................................................................37
6 Package Information ......................................................................................................................... 38
6.1 INDT/R166B....................................................................................................................................38
6.2 INDT/R331B....................................................................................................................................39
7 Ordering and Product Availability .................................................................................................... 40
8 Revision History................................................................................................................................ 40
Date: 2005-03-14 Revision: 0.1
Page 2 of 40

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Preliminary Data Sheet
INDT/R166B
INDT/R331B
1 General Description
The GigaSTaRDigital Display Link is a high-speed serial and long distance link for video, audio and digital data, which
supports the popular VESA and Digital TV standards as well as proprietary video formats from VGA to UXGA with color
depth up to 24 bits.
1.1 Link Interface
The INDT/R166B link requires one single twisted pair cable for the high-speed downlink. The INDT/R331B provides double
bandwidth by using two twisted pairs. Both devices offer an uplink connection using a twisted pair. The downlink must be
established before the uplink can be activated.
VIDEO
AUDIO
SIDEBAND
DATA
M Downlink
U
X
D
E
M
U
X
Only INDT/R330
Uplink
VIDEO
AUDIO
SIDEBAND
DATA
Figure 1.1: GigaSTaRDigital Display Link Interfaces
The transmitter’s and receiver’s generic parallel RGB interfaces (CMOS/TTL compatible) support direct connection to the
parallel data port of any graphic controller or to any flat panel display with a parallel pixel data port. The bit width of the
pixel data path can be scaled to support the 18- or 24-bit mode with 1 pixel/clock, the 36- or 48-bit mode with 2 pixel/clock.
Pixel data can be clocked into the transmitter on the rising, falling or on both edges (18-, 24-bit mode) of the pixel clock.
Pixel data are provided at the receiver on the rising, falling or on both edges (18-, 24-bit mode) of the pixel clock.
1.1.1 Link Interface Bandwidth
The bandwidth of the downlink is shared between video, audio and sideband data. Disabling audio and/or sideband
channels, even partially, increases the available bandwidth for the video data. The video configuration required for VESA
or Digital TV (DTV) / High-Definition TV (HDTV) standard compatible video resolutions is shown in Table 1.1 and Table
1.2.
Mode
1
2
3
4
INDT/R166B configurations
High-speed
Sideband
Low-speed
Sideband
Audio
X X X/
– XX
– ––
X XX
Up to
VESA-/DTV-Mode
XGA 18 color bits
XGA 18 color bits
XGA 24 color bits
480p(60fps), 720p (30fps)
Table 1.1: INDT/R166B Video Configuration
Date: 2005-03-14 Revision: 0.1
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Preliminary Data Sheet
INDT/R166B
INDT/R331B
Mode
1
2
3
4
5
INDT/R331B configurations
High-speed
Sideband
Low-speed
Sideband
Audio
X X X/
– XX
– ––
X XX
X XX
Up to
VESA-/DTV-Mode
SXGA 24 color bits
UXGA 18 color bits
UXGA 18 color bits
720p (60fps)
1080i (30fps)
Table 1.2: INDT/R331B Video Configuration
Note: Implementation of video modes other than VESA or DTV/HDTV is possible. Special modes may need evaluation.
1.2 Pixel Interface
1.2.1 General Information
The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as
graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also
be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI.
PX_CLK+
PX_CLK–
PX_D[47:0]
PX_HSYNC
PX_VSYNC
PX_DE
48
Video
Downstream
INDT
Transmitter
PX_CLK_IN
PX_CLK_OUT
Video
INDR
Receiver
48
PX_CLK
PX_D[47:0]
PX_HSYNC
PX_VSYNC
PX_DE
Figure 1.2: Pixel Interface
Signal
PX_D[47:0]
PX_CLK+
PX_CLK–
PX_CLK
PX_CLK_OUT
PC_CLK_IN
PX_HSYNC
PX_VSYNC
PX_DE
Tx1 Rx Description
IN OUT Configurable parallel pixel data interface
IN OUT Tx Pixel clock 24 – 161 MHz, diff + or single-ended
IN OUT Tx Pixel clock 24 – 161 MHz, diff –
OUT Rx Pixel clock 24 – 161 MHz
OUT Rx Pixel clock 24 – 161 MHz, de-jitter
IN Rx Pixel clock 24 – 161 MHz, de-jitter
IN OUT Pixel data framing – Horizontal sync pulse
IN OUT Pixel data framing – Vertical sync pulse
IN OUT Pixel data framing – Data enable
Table 1.3: Pixel Interface Signals
1 Configurable to 3.3V or 1.8V input levels via VREF-pin.
Date: 2005-03-14 Revision: 0.1
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Preliminary Data Sheet
INDT/R166B
INDT/R331B
The transmitter’s pixel interface accepts pixel data with a pixel clock frequency of 24 – 161 MHz (full pixel mode). For the
Tx side in single-ended mode, PX_CLK+ is the clock input and PX_CLK– has to be tied to GND. A differential pixel clcok
mode on the Rx side is not available. All pixel data and pixel clock inputs of the transmitter can be selected through the
VREF-pin to either work with conventional graphic controllers with 3.3 V output voltage swing or to work with latest
controllers with low voltage swing (1.0 – 2.0 V, see Figure 3.3: VREF Reference Circuitry). The pixel data and pixel
clock outputs of the receiver provide a 3.3 V CMOS compliant output.
1.2.2 Pixel Interface Modes
The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of
the pixel interface is a function of the selected operating mode.
In full-pixel mode the bit width of the pixel interface can be set to support an 18- or 24-bit wide parallel video interface.
1 pixel per sampling edge is transmitted.
In double-pixel mode the bit width of the pixel interface can be set to support a 36- or 48-bit wide parallel video
interface. 2 pixels per sampling edge are transmitted.
1.2.3 Pixel Clock Sampling Modes
The pixel interface can be set to support data sampling at the rising, falling or at both edges of the pixel clock,
depending on the selected mode.
Table 1.4 and , Figure 1.4, Figure 1.5 summarize the various options for configuring the pixel interface.
Pixel Mode
18-bit
(Full Pixel)
24-bit
(Full Pixel)
36-bit
(Double
Pixel)
48-bit
(Double
Pixel)
Clock
Edge
rising
falling
both
rising
falling
both
rising
PX_CLK+
↑↓
↑↓
falling
rising
falling
PX_CLK-
Description
18 bits of pixel(n) sampled at rising edge of PX_CLK+
18 bits of pixel(n) sampled at falling edge of PX_CLK+
18 bits of pixel(n) sampled at both edges of PX_CLK+
24 bits of pixel(n) sampled at rising edge of PX_CLK+
24 bits of pixel(n) sampled at falling edge of PX_CLK+
24 bits of pixel(n) sampled at both edges of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Table 1.4: Overview – Pixel Interface Configurations
Date: 2005-03-14 Revision: 0.1
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