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FEATURES
General
HDMITM/DVI transmitter compatible with HDMI v1.2a,
DVI v1.0, and HDCP 1.1
Internal key storage for HDCP
Single 1.8 V power supply
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
64-lead LFCSP, Pb-free package
Digital video
80 MHz operation supports all resolutions from 480i to
720p/1080i and XGA-75 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, DDR
Supports ITU656 based embedded syncs
Auto input video format timing detection (CEA-861B)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
Supports 8-channel uncompressed LPCM I2S audio up to
192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting
S/PDIF and I2S
On-chip MPU reports HDMI events through interrupts and
registers
APPLICATIONS
DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter
GENERAL DESCRIPTION
The AD9389A-BBCZ is an 80 MHz, high definition multimedia
interface (HDMI) v.1.2a transmitter. It supports HDTV formats
up to 720p/1080i, and computer graphic resolutions up to XGA
(1024 × 768 @ 75 Hz). With the inclusion of HDCP, the AD9389A
allows the secure transmission of protected content as specified
by the HDCP v1.1 protocol.
The AD9389A supports both S/PDIF and 8-channel I2S audio.
Its high fidelity 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
High Performance
HDMI/DVI Transmitter
AD9389A
FUNCTIONAL BLOCK DIAGRAM
SCL SDA
INT
CLK
VSYNC
HSYNC
DE
D[23:0]
S/PDIF
MCLK
I2S[3:0]
LRCLK
SCLK
I2C
SLAVE
REGISTER
CONFIGURATION
LOGIC
HDCP
CORE
INTERRUPT
HANDLER
HDCP-EDID
MICRO-
CONTROLLER
I2C
MASTER
VIDEO
DATA
CAPTURE
COLOR
SPACE
CONVER-
SION
4:2:2 TO
4:4:4
CONVER-
SION
XOR
MASK
HDMI
Tx
CORE
AUDIO
DATA
CAPTURE
AD9389A
Figure 1.
HPD
DDCSDA
DDCSCL
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
audio or compressed audio including Dolby® Digital, DTS®,
and THX®.
The AD9389A helps to reduce system design complexity and
cost by incorporating such features as an internal MPU for
HDCP operations, an I2C master for EDID reading, a single
1.8 V power supply and 5 V tolerance on I2C and hot plug
detect pins.
Fabricated in an advanced CMOS process, the AD9389A is
available in a space saving, 64-lead LFCSP surface-mount
package. The LFCSP package is specified from 0°C to 70°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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AD9389A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Explanation of Test Levels ........................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Applications........................................................................................7
Design Resources ..........................................................................7
Document Conventions ...............................................................7
PCB Layout Recommendations.......................................................8
Power Supply Bypassing ...............................................................8
Digital Inputs .................................................................................8
External Swing Resistor................................................................8
Output Signals ...............................................................................8
Outline Dimensions ..........................................................................9
Ordering Guide .............................................................................9
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 12

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SPECIFICATIONS
Table 1.
Parameter
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case
θJA Junction-to-Ambient
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current, IIL
Input Clamp Voltage
Differential High Level Output Voltage
Differential Output Short-Circuit Current
POWER SUPPLY
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Power-Down Current
Transmitter Supply Current2
Transmitter Total Power
AC SPECIFICATIONS
CLK Frequency
TMDS Output CLK Duty Cycle
Worst Case CLK Input Jitter
Input Data Setup Time
Input Data Hold Time
TMDS Differential Swing
VSYNC and HSYNC Delay from DE Falling
Edge
VSYNC and HSYNC Delay to DE Rising Edge
DE High Time
DE Low Time
Differential Output Swing
Low-to-High Transition Time
High-to-Low Transition Time
AUDIO AC TIMING
Sample Rate
I2S Cycle Time
I2S Setup Time
I2S Hold Time
Audio Pipeline Delay
1 See the Explanation of Test Levels section.
2 Using low output drive strength.
3 UI = unit interval.
Conditions
−16 mA
+16 mA
With active video applied
80 MHz, typical random
pattern
I2S and S/PDIF
Test
Temp Level1
Full VI
Full VI
25°C V
Full VI
Full VI
V
V
Full V
25°C VI
25°C V
25°C V
V
IV
Full IV
Full V
25°C IV
25°C IV
Full VI
25°C IV
25°C IV
Full IV
Full IV
Full IV
VI
VI
VI
25°C VI
25°C VI
25°C VII
25°C VII
Full IV
25°C IV
25°C IV
25°C IV
25°C IV
Rev. 0 | Page 3 of 12
AD9389A
Min Typ Max Unit
1.4 V
0.7 V
3 pF
VDD − 0.1
V
0.4 V
15.2 °C/W
59 °C/W
−25 +25 +90 °C
−10 +10 μA
−0.8 V
+0.8 V
AVCC
V
10 μA
1.71 1.8 1.89 V
50 mV p-p
9 mA
143 155 mA
257 280 mW
13.5 80 MHz
48 52 %
2 ns
1 ns
1 ns
800 1000 1200 mV
1 UI3
1 UI
8191 UI
138 UI
75 490 ps
75 490 ps
32 192 kHz
1 UI
15 ns
0 ns
75 μs

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AD9389A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Digital Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
Rating
5 V to 0.0 V
20 mA
0°C to +70°C
−65°C to +150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design
and characterization testing.
VII. Limits defined by HDMI specification; guaranteed by
design and characterization testing.
ESD CAUTION
Rev. 0 | Page 4 of 12

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9389A
DVDD 1
D0 2
DE 3
HSYNC 4
VSYNC 5
CLK 6
S/PDIF 7
MCLK 8
I2S0 9
I2S1 10
I2S2 11
I2S3 12
SCLK 13
LRCLK 14
PVDD 15
PVDD 16
PIN 1
INDICATOR
AD9389A
TOP VIEW
(Not to Scale)
NC = NO CONNECT
48 DVDD
47 D15
46 D16
45 D17
44 D18
43 D19
42 D20
41 D21
40 D22
39 D23
38 NC
37 NC
36 SDA
35 SCL
34 DDCSDA
33 DDCSCL
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type1
2, 39 to 47,
50 to 63
D[23:0]
I
6 CLK I
3 DE I
4
HSYNC
I
5
VSYNC
I
18 EXT_SW I
20 HPD I
7
S/PDIF
I
8
MCLK
I
9 to 12
I2S[3:0]
I
13
SCLK
I
14
LRCLK
I
26
PD/A0
I
21, 22
TxC−/TxC+ O
31, 32
Tx2−/Tx2+ O
27, 28
Tx1−/Tx1+ O
24, 25
Tx0−/Tx0+ O
32 INT O
19, 23, 29
AVDD
P
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to
5.0 V CMOS logic level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips
digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level.
I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available
through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the
PD/A0 pin state when the supplies are applied to the AD9389A. 1.8 V to 3.3 V CMOS logic level.
Differential Clock Output. Differential clock output at pixel clock rate; transition minimized
differential signaling (TMDS) logic level.
Differential Output Channel 2. Differential output of the red data at 10 × the pixel clock rate;
TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10 × the pixel clock rate;
TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10 × the pixel clock rate;
TMDS logic level.
Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is
recommended.
1.8 V Power Supply for TMDS Outputs.
Rev. 0 | Page 5 of 12