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September 2006
FSB50325S
Smart Power Module (SPM)
Features
• 250V 1.5A 3-phase FRFET inverter including high voltage
integrated circuit (HVIC)
• 3 divided negative dc-link terminals for inverter current sens-
ing applications
• HVIC for gate driving and undervoltage protection
• 3/5V CMOS/TTL compatible, active-high interface
• Optimized for low electromagnetic interference
• Isolation voltage rating of 1500Vrms for 1min.
• Surface mounted device package
• Moisture Sensitive Level 3
General Description
FSB50325S is a tiny smart power module (SPM) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery MOSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving. FSB50325S
provides low electromagnetic interference (EMI) characteristics
with optimized switching speed. Moreover, since it employs
FRFET as a power switch, it has much better ruggedness and
larger safe operation area (SOA) than that of an IGBT-based
power module or one-chip solution. The package is optimized
for the thermal performance and compactness for the use in the
built-in motor application and any other application where the
assembly space is concerned. FSB50325S is the most solution
for the compact inverter providing the energy efficiency,
compactness, and low electromagnetic interference.
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
VPN
ID25
ID80
IDP
PD
VCC
VBS
VIN
TJ
TSTG
RθJC
DC Link Input Voltage,
Drain-source Voltage of each FRFET
Each FRFET Drain Current, Continuous
Each FRFET Drain Current, Continuous
Each FRFET Drain Current, Peak
Maximum Power Dissipation
Control Supply Voltage
High-side Bias Voltage
Input Signal Voltage
Operating Junction Temperature
TC = 25°C
TC = 100°C
TC = 25°C, PW < 100µs
TC = 25°C, Each FRFET
Applied between VCC and COM
Applied between VB(U)-U, VB(V)-V, VB(W)-W
Applied between IN and COM
250
1.5
1.0
3.0
12
20
20
-0.3 ~ VCC+0.3
-20 ~ 150
Storage Temperature
Junction to Case Thermal Resistance
Each FRFET under inverter operating con-
dition (Note 1)
-50 ~ 150
10.2
VISO Isolation Voltage
60Hz, Sinusoidal, 1 minute, Connection pins
to heatsink
1500
Units
V
A
A
A
W
V
V
V
°C
°C
°C/W
Vrms
©2006 Fairchild Semiconductor Corporation
FSB50325S Rev. A
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Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pin Name
COM
VB(U)
VCC(U)
IN(UH)
IN(UL)
NC
VB(V)
VCC(V)
IN(VH)
IN(VL)
NC
VB(W)
VCC(W)
IN(WH)
IN(WL)
NC
P
U, VS(U)
NU
NV
V, VS(V)
NW
W, VS(W)
Pin Description
IC Common Supply Ground
Bias Voltage for U Phase High Side FRFET Driving
Bias Voltage for U Phase IC and Low Side FRFET Driving
Signal Input for U Phase High-side
Signal Input for U Phase Low-side
No Connection
Bias Voltage for V Phase High Side FRFET Driving
Bias Voltage for V Phase IC and Low Side FRFET Driving
Signal Input for V Phase High-side
Signal Input for V Phase Low-side
No Connection
Bias Voltage for W Phase High Side FRFET Driving
Bias Voltage for W Phase IC and Low Side FRFET Driving
Signal Input for W Phase High-side
Signal Input for W Phase Low-side
No Connection
Positive DC–Link Input
Output for U Phase & Bias Voltage Ground for High Side FRFET Driving
Negative DC–Link Input for U Phase
Negative DC–Link Input for V Phase
Output for V Phase & Bias Voltage Ground for High Side FRFET Driving
Negative DC–Link Input for W Phase
Output for W Phase & Bias Voltage Ground for High Side FRFET Driving
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(6) VS(U)
(7) VB(V)
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
(11) VS(V)
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(16) VS(W)
VCC
HIN
LIN
COM
VB
HO
VS
LO
VCC
HIN
LIN
COM
VB
HO
VS
LO
VCC
HIN
LIN
COM
VB
HO
VS
LO
(17) P
(18) U
(19) NU
(20) NV
(21) V
(22) NW
(23) W
Note:
Source terminal of each MOSFET is not connected to supply ground or bias voltage ground inside SPM. External connections should be made as indicated in Figure 2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
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Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Inverter Part (Each FRFET Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min Typ Max Units
BVDSS
Drain-Source
Voltage
Breakdown
VIN= 0V, ID = 250µA (Note 2)
250 -
-
V
BVDSS/
TJ
IDSS
Breakdown Voltage
perature Coefficient
Tem-
ID = 250µA, Referenced to 25°C
Zero Gate Voltage
Drain Current
VIN= 0V, VDS = 250V
- 0.31 -
- - 250
V
µA
RDS(on)
Static Drain-Source
On-Resistance
VCC = VBS = 15V, VIN = 5V, ID = 1.0A
- 1.4 1.8
VSD
Drain-Source Diode
Forward Voltage
VCC = VBS = 15V, VIN = 0V, ID = -1.0A
- - 1.2 V
tON
tOFF
trr
EON
EOFF
RBSOA
Switching Times
VPN = 150V, VCC = VBS = 15V, ID = 1.0A
VIN = 0V 5V
Inductive load L=3mH
High- and low-side FRFET switching
(Note 3)
Reverse-bias
ating Area
Safe
Oper-
VPN = 200V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS,
TJ = 150°C
High- and low-side FRFET switching (Note 4)
- 1076 -
- 660 -
- 108 -
- 47 -
- 3.1 -
ns
ns
ns
µJ
µJ
Full Square
Control Part (Each HVIC Unless Otherwise Specified)
Symbol
Parameter
Conditions
IQCC
IQBS
UVCCD
UVCCR
UVBSD
UVBSR
VIH
VIL
IIH
IIL
Quiescent VCC Current
Quiescent VBS Current
Low-side Undervoltage
Protection (Figure 6)
High-side Undervoltage
Protection (Figure 7)
ON Threshold Voltage
OFF Threshold Voltage
Input Bias Current
VCC=15V, VIN=0V Applied between VCC and COM
VBS=15V, VIN=0V
Applied between VB(U)-U,
VB(V)-V, VB(W)-W
VCC Undervoltage Protection Detection Level
VCC Undervoltage Protection Reset Level
VBS Undervoltage Protection Detection Level
VBS Undervoltage Protection Reset Level
Logic High Level
Applied between IN and COM
Logic Low Level
VIN = 5V
VIN = 0V
Applied between IN and COM
Min Typ Max Units
- - 160 µA
- - 100 µA
7.4 8.0 9.4
8.0 8.9 9.8
7.4 8.0 9.4
8.0 8.9 9.8
3.0 -
-
- - 0.8
- 10 20
- -2
V
V
V
V
V
V
µA
µA
Note:
1. For the measurement point of case temperature TC, please refer to Figure 3 in page 4.
2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM. VPN should be sufficiently less than this value considering the
effect of the stray inductance so that VDS should not exceed BVDSS in any case.
3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test cir-
cuit that is same as the switching test circuit.
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Recommended Operating Conditions
Symbol
Parameter
Conditions
VPN
VCC
VBS
VIN(ON)
VIN(OFF)
tdead
fPWM
Supply Voltage
Applied between P and N
Control Supply Voltage
High-side Bias Voltage
Input ON Threshold Voltage
Input OFF Threshold Voltage
Applied between VCC and COM
Applied between VB and output(U, V, W)
Applied between IN and COM
Blanking Time for Preventing
Arm-short
VCC=VBS=13.5 ~ 16.5V, TJ 150°C
PWM Switching Frequency TJ 150°C
Min.
-
13.5
13.5
3.0
0
Value
Typ.
150
15
15
-
-
Max.
200
16.5
16.5
VCC
0.6
Units
V
V
V
V
V
1.0 -
- µs
- 15 - kHz
15-V Line
These values depend on PWM
control algorithm
R2
Micom
R1 D1
R5
C5
VCC
HIN
LIN
COM
VB
HO
VS
LO
P VDC
Inverter
Output
C3
N R3
HIN LIN Output
Note
0 0 Z Both FRFET Off
01
0 Low-side FRFET On
1 0 VDC High-side FRFET On
1
1 Forbidden
Shoot-through
10µF
C2 C1
One-Leg Diagram of SPM
Open Open
Z
Same as (0, 0)
* Example of bootstrap paramters:
C1 = C2 = 1µF ceramic capacitor,
R1 = 56Ω, R2 = 20
Note:
(1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 400-V rating
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
(3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM is compatible with stan-
dard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
14.50mm
3.80mm
Note:
MOSFET
Case Temperature(Tc)
Detecting Point
Attach the thermocouple on top of the heatsink-side of SPM (between SPM and heatsink if applied) to get the correct temperature measurement.
Figure 3. Case Temperature Measurement
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VIN VIN
Irr
100% of ID
VDS
120% of ID
ID
10% of ID
ID VDS
tON trr
tOFF
(a) Turn-on
(b) Turn-off
Figure 4. Switching Time Definition
VCC
RBS
REH
VCC
HIN
LIN
COM
VB
HO
VS
LO
L
+
VDS
-
ID
VDC
CBS One-leg Diagram of SPM
Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Input Signal
UV Protection
Status
Low-side Supply, VCC
RESET
UVCCD
DETECTION
UVCCR
RESET
MOSFET Current
Figure 6. Undervoltage Protection (Low-side)
Input Signal
UV Protection
Status
High-side Supply, VBS
RESET
UVBSD
DETECTION
UVBSR
RESET
MOSFET Current
Figure 7. Undervoltage Protection (High-side)
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