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Data Sheet
ISL6545, ISL6545A
March 3, 2011
FN6305.6
5V or 12V Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller
The ISL6545, ISL6545A makes simple work out of
implementing a complete control and protection scheme for a
DC/DC stepdown converter driving N-Channel MOSFETs in a
synchronous buck topology. Since it can work with either 5V or
12V supplies, this one IC can be used in a wide variety of
applications within a system. The ISL6545, ISL6545A
(hereafter referred to as “ISL6545x”, except as needed)
integrates the control, gate drivers, output adjustment,
monitoring and protection functions into a single 8 Ld SOIC or
10 Ld DFN package.
The ISL6545x provides single feedback loop, voltage-mode
control with fast transient response. The output voltage can be
precisely regulated to as low as 0.6V, with a maximum
tolerance of ±1.0% over-temperature and line voltage
variations. A selectable fixed frequency oscillator (ISL6545 for
300kHz; ISL6545A for 600kHz) reduces design complexity,
while balancing typical application cost and efficiency.
The error amplifier features a 20MHz gain-bandwidth
product and 9V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the lower MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Pinout
ISL6545, ISL6545A
(8 LD SOIC)
TOP VIEW
BOOT 1
UGATE 2
GND 3
LGATE/OCSET 4
8 PHASE
7 COMP/SD
6 FB
5 VCC
ISL6545, ISL6545A
(10 LD 3x3 DFN)
TOP VIEW
BOOT 1
UGATE 2
N/C 3
GND 4
LGATE/OCSET 5
GND
10 PHASE
9 COMP/SD
8 FB
7 N/C
6 VCC
Features
• Operates from +5V or +12V Supply Voltage (for bias)
- 1.0V to 12V VIN Input Range (up to 20V possible with
restrictions; see Input Voltage Considerations)
- 0.6V to VIN Output Range
- Integrated Gate Drivers use VCC (5V to 12V)
- 0.6V Internal Reference; ±1.0% tolerance
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
- Drives N-Channel MOSFETs
- Traditional Dual Edge Modulator
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Lower MOSFET’s rDS(ON)
• Small Converter Size in 8 Ld SOIC or 10 Ld DFN
- 300kHz or 600kHz Fixed Frequency Oscillator
- Fixed Internal Soft-Start, Capable into a Pre-biased
Load
- Integrated Boot Diode
- Enable/Shutdown Function on COMP/SD Pin
- Output Current Sourcing and Sinking
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies for Microprocessors or Peripherals
- PCs, Embedded Controllers, Memory Supplies
- DSP and Core Communications Processor Supplies
• Subsystem Power Supplies
- PCI, AGP; Graphics Cards; Digital TV
- SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus
Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• Industrial Power Supplies; General Purpose Supplies
• 5V or 12V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2006, 2007, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL6545, ISL6545A
*
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
FIXED FREQUENCY
OSCILLATOR
(kHz)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6545CBZ
6545 CBZ
300
0 to +70
8 Ld SOIC
M8.15
ISL6545ACBZ
6545 ACBZ
600
0 to +70
8 Ld SOIC
M8.15
ISL6545IBZ
6545 IBZ
300
-40 to +85
8 Ld SOIC
M8.15
ISL6545AIBZ
6545 AIBZ
600
-40 to +85
8 Ld SOIC
M8.15
ISL6545CRZ
545Z
300
0 to +70
10 Ld DFN
L10.3x3C
ISL6545ACRZ
45AZ
600
0 to +70
10 Ld DFN
L10.3x3C
ISL6545IRZ
45IZ
300
-40 to +85
10 Ld DFN
L10.3x3C
ISL6545AIRZ
5ARZ
600
-40 to +85
10 Ld DFN
L10.3x3C
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6545, ISL6545A. For more information on MSL please see
techbrief TB363.
2 FN6305.6
March 3, 2011

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ISL6545, ISL6545A
Block Diagram
VCC
SAMPLE
AND
HOLD
POR AND
INTERNAL
+
-
OC
SOFT-START
REGULATOR
COMPARATOR
5V int.
DBOOT
FB
COMP/SD
21.5µA
TO
LGATE/OCSET
5V int.
20μA
ERROR
AMP
0.6V
+
-
PWM
COMPARATOR
+
-
0.4V + DIS
-
OSCILLATOR
FIXED 300 (or 600)kHz
20kΩ
INHIBIT
GATE
CONTROL
PWM LOGIC
DIS
VCC
BOOT
UGATE
PHASE
LGATE/OCSET
Typical Application
VCC
5V OR 12V
RF
CF
ROFFSET
CDCPL
COMP/SD
VCC
51
ISL6545,
ISL6545A
8
7
2
BOOT
PHASE
UGATE
CBOOT
CI
6
FB
Type II
compensation
shown
LGATE/OCSET
34
GND
ROCSET
RS
GND
VIN
1V TO 12V
CHF
CBULK
LOUT
COUT
+VO
3 FN6305.6
March 3, 2011

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ISL6545, ISL6545A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V
BOOT Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 36V
UGATE Voltage VUGATE . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT +0.3V
LGATE/OCSET Voltage, VLGATE/OCSET GND - 0.3V to VCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VCC + 0.3V
PHASE Voltage, VPHASE . . . . . . . . . .GND - 0.3V to VBOOT + 0.3V
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND <36V)
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . .15V
-0.3V to 16V (<10ns, 10µJ)
Clamp Voltage, VBOOT - VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
FB, COMP/SD Voltage. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
SOIC Package (Note 4) . . . . . . . . . . . . . .
95
N/A
DFN Package (Notes 5, 6). . . . . . . . . . . .
44
5.5
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage, VCC . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V
Ambient Temperature Range
ISL6545C, ISL6545AC. . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6545I, ISL6545AI . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air, with “direct attach” features. See
Tech Brief TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Input Bias Supply Current
POWER-ON RESET
Rising VCC POR Threshold
VCC POR Threshold Hysteresis
OSCILLATOR
Switching Frequency
Ramp Amplitude
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
GATE DRIVERS
Upper Gate Source Impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
VCC = 12V, TJ = 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 7) TYP (Note 7)
IVCC
VCC = 12V; disabled
VPOR
4 5.2 7
3.9 4.1 4.3
0.30 0.35 0.40
fOSC
fOSC
ΔVOSC
ISL6545C
ISL6545I
ISL6545AC
ISL6545AI
VREF
ISL6545C
ISL6545I
GAIN
GBWP
SR
270 300 330
240 300 330
540 600 660
510 600 660
1.5
-1.0 - +1.0
-1.5 - +1.5
0.600
96
20
9
RUG-SRCh
RUG-SNKh
RLG-SRCh
RLG-SNKh
VCC = 14.5V; I = 50mA
VCC = 14.5V; I = 50mA
VCC = 14.5V; I = 50mA
VCC = 14.5V; I = 50mA
3.0
2.7
2.4
2.0
UNITS
mA
V
V
kHz
kHz
kHz
kHz
VP-P
%
%
V
dB
MHz
V/µs
Ω
Ω
Ω
Ω
4 FN6305.6
March 3, 2011

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ISL6545, ISL6545A
Electrical Specifications VCC = 12V, TJ = 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 7) TYP (Note 7)
Upper Gate Source Impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
RUG-SRCl
RUG-SNKl
RLG-SRCl
RLG-SNKl
VCC = 4.25V; I = 50mA
VCC = 4.25V; I = 50mA
VCC = 4.25V; I = 50mA
VCC = 4.25V; I = 50mA
3.5
2.7
2.75
2.1
OCSET Current Source
IOCSET
ISL6545C; LGATE/OCSET = 0V
ISL6545I; LGATE/OCSET = 0V
19.5
18.0
21.5
21.5
23.5
23.5
Disable Threshold (COMP/SD pin)
VDISABLE
0.375 0.400
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
0.425
UNITS
Ω
Ω
Ω
Ω
µA
µA
V
Functional Pin Description (SOIC, DFN)
VCC (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL6545x, as well
as the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if VCC rises above 6.5V (but the LGATE/OCSET and
BOOT will still be sourced by VCC). Connect a well-
decoupled 5V or 12V supply to this pin.
FB (SOIC Pin 6, DFN Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/SD pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from the output to GND is used to set the regulation voltage.
GND (SOIC Pin 3, DFN Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available. For the DFN package,
Pin 4 MUST be connected for electrical GND; the metal pad
under the package should also be connected to the GND
plane for thermal conductivity.
PHASE (SOIC Pin 8, DFN Pin 10)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (SOIC Pin 2, DFN Pin 2)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-channel MOSFET (equal to VCC minus
the on-chip BOOT diode voltage drop), with respect to PHASE.
COMP/SD (SOIC Pin 7, DFN Pin 9)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/SD low (VDISABLE = 0.4V nominal) will
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external
pull-down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20µA
current source will continue to draw current.
When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20µA charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the VDISABLE trip point, the
ISL6545x will begin a new Initialization and soft-start cycle.
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from VCC). This pin is also
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (ROCSET) from this pin to GND. See
“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
N/C (DFN only; Pin 3, Pin 7)
These two pins in the DFN package are No Connect.
5 FN6305.6
March 3, 2011