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U2752M
Digital I/Q-Generator Chip for DAB
Description
The U2752M is an integrated circuit in CMOS
technology for splitting a digital DAB signal into its
quadrature components. The device is designed for DAB
(ETS 300 401) applications.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D U2752M splits a digital DAB input signal into its
quadrature components
D Quadrature matching: 0 dB in magnitude,
1.6° in phase
D Clock frequency: 4.096 MHz
D Input signal
– Center frequency: 3.072 MHz
Bandwidth: 1.536 MHz
Data format:
8 bit, 4.096 MHz in 2’s complement representation
D Output signal
– Select pin for baseband or 1.024-MHz center
frequency
I-, Q- components in time multiplex
Data format:
8 bit, 4.096 MHz in 2’s complement representation
Block Diagram
8 DATA_IN
RESET
CLOCK
2 AP–I
MUX
2 AP–Q
IQDATA 7
DATA_RI
VDD VSS
Figure 1. Block diagram
96 12265
MIX_OFF
Ordering Information
Extended Type Number
U2752M-AFL
U2752M-AFLG3
Package
SO24
SO24
Remarks
Taping according to IEC-286-3
Rev. A1, 29-Jun-98
Preliminary Information
1 (6)

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U2752M
Pin Description
Pin Signal
Description
PAD Type
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1
MIX_OFF
Low: I/Q in baseband representation, High. I/Q in IF representation
BUFINCDN
2
RESET
Reset signal, high active
BUFINCDN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ3 VSS Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ4
DATA_IN0
Data input (LSB)
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ5
DATA_IN1
Data input
BUFINMOS
6
DATA_IN2
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ7
DATA_IN3
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ8
DATA_IN4
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ9
DATA_IN5
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ10
DATA_IN6
Data input
BUFINMOS
11
DATA_IN7
Data input (MSB)
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ12 VSS Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ13
CLOCK
System clock 4.096 MHz
BUFTGMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ14
DATA_RI
Internal data_ri signal
BU2OUT
15
VDD
Power supply
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ16
IQDATA7
Data_output, I and Q multiplex (MSB)
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ17
IQDATA6
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ18
IQDATA5
Data_output, I and Q multiplex
BU2OUT
19
IQDATA4
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ20
IQDATA3
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ21
IQDATA2
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ22
IQDATA1
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ23
IQDATA0
Data_output, I and Q multiplex (LSB)
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ24
VDD
Power supply
MIX_OFF 1
RESET 2
24 VDD
23 IQDATA0
VSS 3
22 IQDATA1
DATA_IN0 4
DATA_IN1 5
21 IQDATA2
20 IQDATA3
DATA_IN2 6
19 IQDATA4
DATA_IN3 7
18 IQDATA5
DATA_IN4 8
17 IQDATA6
DATA_IN5 9
16 IQDATA7
DATA_IN6 10
15 VDD
DATA_IN7 11
14 DATA_RI
VSS 12
13 CLOCK
96 12266
Figure 2. Pinning
Functional Description
The U2752M generates the in-phase and quadrature
components of the DAB input signal with a quadrature
matching of 0 dB in magnitude and a maximum value of
1.6° in phase. The clock of the device is 4.096 MHz.
The data format of the input signal DATA_IN is 8 bits,
sampled with 4.096 MHz in 2’s complement represen-
tation. Its center frequency is 3.072 MHz with a
bandwidth of 1536 MHz. The U2752M uses decimation
and common filter techniques to generate the quadrature
components.
The output interface consists of the split signal IQDATA
with a data format of 8 bits, 4.096 MHz in 2’s comple-
ment representation. The in-phase (I) and quadrature (Q)
components are represented in time division multiplex
format with a selection signal DATA_RI of 4.096 MHz.
The output representation in baseband or 1.024-MHz
center frequency is selected by the MIX_OFF signal. For
utilization together with TEMIC’s U2752M device, the
baseband representation (MIX_OFF = ‘0’) must be
selected.
2 (6)
Rev. A1, 29-Jun-98
Preliminary Information

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Absolute Maximum Ratings
DC supply voltage
Input / output voltage
Storage temperature
Parameters
U2752M
Symbol Min. Typ.
Max.
Unit
VDD
Vin/Vout
Tstg
–0.5
–0.5
–65
+7
VDD + 0.5
+150
V
V
°C
Operating Range
Parameters
DC supply voltage
Input / output voltage
Ambient temperature
Power dissipation (static)
Power dissipation (dynamic)
Symbol Min. Typ. Max. Unit
VDD
Vin/Vout
Tamb
Pstat
Pdyn
4.5
0
–40
5.5 V
VDD
+85
V
°C
0.25 mW
15 mW
Thermal Resistance
Parameters
Junction ambient SO24
Symbol
RthJA
Value
80
Unit
K/W
Electrical Characteristics
Test conditions: VDD = 5 V, Tamb = 25°C
Parameters
Input HIGH voltage
Input LOW voltage
Positive threshold
Negative threshold
Input leakage
Output HIGH voltage
Output LOW voltage
Test Conditions / Pins Symbol Min. Typ. Max. Unit
Pins 1, 2, 4 to 11 VIH
3.5
V
Pins 1, 2, 4 to 11 VIL
1.5 V
Pin 13
VT+ 1.61
2.60 V
VT– 2.47
3.52 V
VIN = VDD or VSS
VIN = VDD
Pins 1, 2, 4 to 11 and 13
IL
±1 ±5 µA
+40 +100 µA
IOH = +6.4 mA
Pins 14, 16 to 23
VOH
2.4
V
IOH = –6.4 mA
Pins 14, 16 to 23
VOL
0.4 V
Rev. A1, 29-Jun-98
Preliminary Information
3 (6)

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U2752M
Input Interface Description
RESET
CLOCK
Internal RI
selection signal
DATA_IN
RI R I
tsu_din
Figure 3. Input interface signals (tsu_din 10 ns)
96 12267
For verification purposes, it can be helpful to know how
the U2752M selects the input samples for real and imagi-
nary data processing.
The U2752M generates an internal real and imaginary
selection signal, which depends on the first recognized
rising CLOCK edge as shown in figure 3. Due to this
selection signal, the data input DATA_IN will be used for
the real or imaginary process path of the IC. The setup
time of DATA_IN tsu_din must be 10 ns.
Results
The phase deviation from 90° of the I- and Q- parts over
the normalized frequency is shown in figure 4.
The DAB-relevant frequency range is from 1/8 to 7/8 on
the normalized frequency axis.
For the DAB frequency range, the maximum phase mis-
match is 1.6° and the amplitude mismatch is 0 dB.
100
80 max. phase mismatch = 1.6 deg
60 max. amplitude mismatch = 0 dB
40
20
0
–20
–40
–60
–80
–100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
96 12047
Normalized frequency
Figure 4. Phase deviation of the I- and Q–parts
4 (6)
Rev. A1, 29-Jun-98
Preliminary Information

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Package Information
Package SO24
Dimensions in mm
15.55
15.30
0.4
1.27
24
13.97
2.35
0.25
0.10
13
U2752M
9.15
8.65
7.5
7.3
10.50
10.20
0.25
technical drawings
according to DIN
specifications
13037
1 12
Rev. A1, 29-Jun-98
Preliminary Information
5 (6)