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SY89312V
3.3V/5V, 4GHz PECL/ECL
÷2 Clock Generator
Precision Edge®
General Description
The SY89312V is an integrated ÷2 divider with differential
clock inputs. It is functionally equivalent to the
SY100EP32V but in an ultra-small 8-pin QFN package
that features a 70% smaller footprint.
The VBB pin, an internally generated voltage supply, is
available for this device only. For single-ended input
conditions, the unused differential input is connected to VBB
as a switching reference voltage. VBB can also bias AC-
coupled inputs. When used, decouple VBB and VCC via a
0.01µF capacitor and limit current sourcing or sinking to
0.5mA. When not in use, VBB should be left open.
The reset pin is asynchronous and is asserted when it is
high. Upon power-up, the internal flip-flops will be in a
random state; the reset allows for the synchronous use of
multiple SY89312Vs in a system.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Precision Edge®
Features
Guaranteed AC performance over temperature and
voltage:
>4GHz fMAX input
<160ps tr/tf
<440ps tpd
3.3V and 5V power supply operation
100k ECL/PECL-compatible I/O
Internal 75Kinput pull-down resistors
Wide operating temperature range: –40°C to +85°C
Available in ultra-small 8-pin 2mm × 2mm QFN package
Truth Table(1)
CLK
X
/CLK
X
Note:
1. F = Divide by 2 function.
RESET
H
L
Q
L
F
/Q
H
F
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 25, 2013
Revision 2.0
hbwhelp@micrel.com or (408) 955-1690

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Micrel, Inc.
SY89312V
Ordering Information
Part Number
SY89312VMGTR(2)
Package Type
8-pin 2mm × 2mm QFN
Note:
2. Pb-Free package is recommended for new designs.
Operating Range
Industrial
Package Marking
312 with Pb-Free Bar Line Indicator
Lead Finish
Pb-Free NiPdAu
Pin Configuration
8-Pin 2mm × 2mm QFN
Pin Description
Pin Number
2, 3
7, 6
8
5
4
1
Pin Name
CLK, /CLK
Q, /Q
VCC
VEE, ePad
VBB
Reset
Type
Pin Function
100K
ECL/PECL
Input
Differential PECL/ECL Input: Internal 75kΩ pull-down resistor. If left open, pin
defaults LOW (see Input Interface Applications section for single-ended inputs).
100K
ECL/PECL
Output
Differential PECL/ECL Output: Output CLK input divided by 2 (see Output
Interface Applications section for recommendations on terminations).
Positive Power
Supply
Positive Power Supply: Bypass with 0.1
citoFr/s/0..01F low ES
Negative Negative Power Supply: VEE and exposed pad (ePad) must be tied to most
Power Supply negative supply. For PECL/LVPECL connect to ground.
Reference
Voltage
Output
Bias Reference Voltage: VCC–1.4V. Used as reference voltage for single- ended
inputs or AC-coupling to the CLK, /CLK inputs. Maximum sink/source is ±0.5mA
(see Input Interface Applications section).
100k
ECL/PECL
Input
Single-Ended Input: PECL/ECL asynchronous reset.
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Micrel, Inc.
SY89312V
Absolute Maximum Ratings(3)
Supply Voltage (VCC VEE) .....................................+6.0V
Input Voltage (VIN) ............................................ 0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ............................................................ 50mA
Surge ..................................................................100mA
Current (VBB)
Source or Sink on VBB(6).....................................±1.5mA
Lead Temperature (soldering, 20s)............................ 260°C
Storage Temperature (Ts)......................... 65°C to +150°C
Operating Ratings(4)
Supply Voltage (VCC VEE) .........................+3.0 to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(5)
QFN (θJA)
Still Air .........................................................93°C/W
500lfpm .......................................................87°C/W
QFN (ψJB)
Junction-to-Board ........................................ 56°C/W
PECL/ECL (100K) DC Electrical Characteristics
VCC = +3.3V ±10% or +5V ±10% and VEE = 0V; VCC = 0V and VEE = –3.3V ±10% or –5V ±10%; RL = 50Ω to VCC – 2V;
TA = –40°C to +85°C unless otherwise stated.
Symbol Parameter
Condition
Min.
Typ.
Max.
IEE Power Supply Current
Maximum VCC, no load
30
42
VOH Output HIGH Voltage
VCC – 1.145 — VCC – 0.895
VOL Output LOW Voltage
VCC – 1.945 — VCC – 1.695
VIH Input HIGH Voltage
VCC – 1.225
VCC – 0.88
VIL Input LOW Voltage
VCC – 1.945 — VCC – 1.625
VIHCMR
Input HIGH Voltage Common
Mode Range(7)
VEE + 2.0
VCC
VBB Bias Voltage
VCC – 1.525 VCC – 1.425 VCC – 1.325
Units
mA
V
V
V
V
V
V
IIH Input HIGH Current
— — 150 A
Input LOW Current CLK
IIL
Input LOW Current /CLK
0.5
–150
A
Notes:
3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
4. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
5. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
6. Due to the limited drive capability use for input of the same package only.
7. VIHCMR (minimum) varies 1:1 with VEE, (maximum) varies 1:1 with VCC.
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Micrel, Inc.
SY89312V
AC Electrical Characteristics(8)
PECL: VCC = +3.3V ±10% or +5V ±10% and VEE = GND; ECL: VEE = –3.3V ±10% or –5V ±10% and VCC = GND; RL = 50to VCC – 2V;
TA = –40°C to +85°C unless otherwise stated.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
fMAX Maximum Input Frequency
Propagation Delay to Output
tpd Differential RESET, CLK Q, /Q
4 — — GHz
250 275 440 ps
tRR Set/Reset Recovery
200 100
— ps
tPW Minimum Pulse Width RESET
550 200
— ps
tJITTER
Cycle-to-Cycle RMS Jitter
— — 1 psRMS
VPP Input Voltage Swing (Differential)
150
800
1200
mV
tr, tf Output Rise/Fall Times Q, /Q (20% to 80%)
Note:
8. Measured using a 750mV source, 50% duty cycle clock source
50 100 160 ps
Timing Diagram
Input Interface Applications
Figure 1. Single-Ended LVPECL Input (Terminating Unused Input)
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Micrel, Inc.
LVPECL Output Interface Applications
SY89312V
Figure 2. Parallel Thevenin-Equivalent Termination
Figure 3. Three Resistor “Y Termination”
June 25, 2013
Figure 4. Terminating Unused I/O
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