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Preliminary Technical Data
4 ADC/8 DAC with PLL,
192 kHz, 24 Bit CODEC
AD1935/AD1936/AD1937/AD1938/AD1939
Features
PLL generated (32-192kHz) or direct master clock
Low EMI design
109 dB DAC/ 107dB ADC Dynamic Range and SNR
-94dB THD+N
Single 3.3V Supply
Tolerance for 5V logic inputs
Supports 24-bits and 8 kHz - 192 kHz sample rates
Differential ADC input
Single-ended or Differential DAC output versions
Log volume control with "auto-ramp" function
Hardware and software controllable clickless mute
Software and hardware power-down
Right justified, left justified, I2S and TDM Modes
Master and slave modes up to 16 channel in/out
48-lead LQFP or 64-lead LQFP plastic package
Applications
Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors
GENERAL DESCRIPTION
The AD193X family are high performance, single-chip codecs that
provide 4 ADCs with differential input and 8 DACs with either
single-ended or differential output using ADI’s patented multibit
sigma-delta architecture. An SPI® or I2C® port is included, allowing
a microcontroller to adjust volume and many other parameters.
The AD193X family operates from 3.3V digital and analog supplies.
The AD193X is available in a 48-lead (SE output) or 64-lead
(differential output) LQFP package.
The AD193X is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures. By
using the on-board PLL to derive master clock from L-R clock, the
AD193X eliminates the need for a separate high frequency master
clock. It can also be used with a suppressed bit clock. The D-A and
A-D converters are designed using the latest ADI continuous time
architectures to further minimize EMI. By using 3.3V supplies,
power consumption is minimized, further reducing emissions.
Functional Block Diagram
Digital Audio
Input/Output
Analog
Audio
Inputs
AD193X
Serial Data Port
ADC
SDATAOUT
SDATAIN Digital
Digital
Filter
ADC Filter
&
ADC
CLOCKS
Volume
Control
ADC Timing Management
&
Control
(Clock & PLL)
Precision
Voltage
Reference
Control Port
SPI / I2C
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
Analog
Audio
Outputs
Control Data
Input/Output
Figure 1
Rev. PrI
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.

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AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
AD193X—SPECIFICATIONS
Test Conditions, Unless Otherwise Noted.
Performance of all channels is identical (exclusive of the Inter-channel Gain Mismatch and Inter-channel Phase Deviation specifications).
Parameter
Supply Voltages (AVDD, DVDD)
Case Temperature
Master Clock
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance (Digital Output)
Load Current (Digital Output)
Input Voltage HI
Input Voltage LO
Rating
3.3 V
25°C
12.288 MHz (48 kHz fS, 256 × fS Mode)
1.000 kHz, 0 dBFS (Full Scale), -1 dBVrms (0.9Vrms)
48 kHz
20 Hz to 20 kHz
24 Bits
50 pF
±1 mA or 1.5kto ½ DVDD supply
2.0 V
0.8 V
Table 1
Analog Performance
Parameter
ANALOG-TO-DIGITAL CONVERTERS
DIGITAL-TO-ANALOG CONVERTERS
ADC Resolution (all ADCs)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Avg)
Total Harmonic Distortion + Noise (–1 dBFS)1
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR, 100 mV RMS, 1 kHz
CMRR, 100 mV RMS, 20 kHz
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1
No Filter (RMS), Single-ended version
With A-Weighted Filter (RMS), Single-ended version
With A-Weighted Filter (Avg), Single-ended version
No Filter (RMS), Differential version
With A-Weighted Filter (RMS), Differential version
With A-Weighted Filter (Avg), Differential version
Total Harmonic Distortion + Noise (0 dBFS)1
Single-ended version
Differential version
Full-Scale Output Voltage (Single-ended version)
Full-Scale Output Voltage (Differential version)
Gain Error
Min Typ
24
102
105
107
–92
1.9
–5.0
–0.1
–10 0
100
–110
70
70
14
10
1.5
101
104
106
104
107
109
–92
–94
0.9 (2.5)
1.8 (5.0)
-6% TBD
Max Unit
Bits
dB
dB
dB
dB
V rms
+5.0 %
+0.1 dB
+10 mV
ppm/°C
dB
dB
dB
k
pF
V
dB
dB
dB
dB
dB
dB
dB
dB
V rms (V pp)
V rms (V pp)
+6% %
1 Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active.
Rev. PrI | Page 2 of 30

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Preliminary Technical Data
AD1935/AD1936/AD1937/AD1938/AD1939
Parameter
REFERENCE
Interchannel Gain Mismatch
Offset Error, Single-ended version
Offset Error, Differential version
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
Internal Reference Voltage, FILTR
External Reference Voltage, FILTR
Common-Mode Reference Output, CM
Table 2
Crystal Oscillator
Parameter
Transconductance
Table 3
Digital I/O
Parameter
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 4 mA
Low Level Output Voltage (VOL) IOL = 4 mA
Input Capacitance
Min
2.0
DVDD – 0.5
Table 4
Power Supplies
Parameter
Supplies
Dissipation
Power Supply Rejection Ratio
Voltage, DVDD
Voltage, AVDD
Digital Current
Digital Current—Power-Down
Digital Current—Reset
Analog Current
Analog Current—Power-Down
Analog Current—Reset
Operation—All Supplies
Operation—Digital Supply
Operation—Analog Supply
Power-Down—All Supplies
1 kHz 200 mV p-p Signal at Analog Supply Pins
20 kHz 200 mV p-p Signal at Analog Supply Pins
Table 5
Min Typ
-0.5
-15
-10
-30
100
0
0.375
95
100
1.50
0.90 1.50
1.50
Max Unit
+0.5 dB
mV
mV
30 ppm/°C
dB
Degrees
dB
dB
±0.6 dB
V
1.80 V
V
Min Typ
10
Max Unit
mmhos
Typ Max
0.8
10
10
0.5
5
Unit
V
V
µA
µA
V
V
pF
Min Typ
3.0 3.3
3.0 3.3
56
TBD
TBD
74
TBD
TBD
429
185
244
TBD
TBD
TBD
Max Unit
3.6 V
3.6 V
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
dB
dB
Rev. PrI | Page 3 of 30

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AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
Temperature Range
Parameter
Specifications Guaranteed
Functionality Guaranteed
Storage
Min
–40
–40
–65
Table 6
Typ
25
Max
+105
+125
+150
Unit
°C Case
°C Ambient
°C Case
°C
Digital Filters
Mode
ADC
DECIMATION
FILTER
All Modes,
Typ @ 48 kHz
48 kHz Mode,
Typ @ 48 kHz
DAC
INTERPOLATION
FILTER
96 kHz Mode,
Typ @ 96 kHz
192 kHz Mode,
Typ @ 192 kHz
Timing Specifications
Parameter
MASTER CLOCK AND RESET
SPI PORT
Parameter
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Table 7
Factor
0.4375 fS
Min
0.5 fS
0.5625 fS
22.9844/ fS
0.4535 fS
79
0.5 fS
0.5465 fS
25/ fS
0.3646 fS
70
0.5 fS
0.6354 fS
11/ fS
0.3646 fS
70
0.5 fS
0.6354 fS
8/ fS
70
Comments
tMH MCLK High
PLL Mode
tML MCLK Low
PLL Mode
tMCLK
MCLK Period
PLL Mode, 256 fS reference
fMCLK MCLK Frequency PLL Mode, 256 fS reference
tMH MCLK High
Direct 512 fS Mode
tML MCLK Low
Direct 512 fS Mode
tMCLK
MCLK Period
Direct 512 fS Mode
fMCLK MCLK Frequency Direct 512 fS Mode
tPDR PD/RST Low
tPDRR PD/RST Recovery Reset to Active Output
tCCH CCLK High
tCCL CCLK Low
tCCP CCLK Period
Rev. PrI | Page 4 of 30
Typ
21
±0.015
24
27
479
22
24
26
521
35
48
61
115
70
96
122
42
Max
±0.01
±0.05
±0.1
Unit
kHz
dB
kHz
kHz
dB
µs
kHz
dB
kHz
kHz
dB
µs
kHz
dB
kHz
kHz
dB
µs
kHz
dB
kHz
kHz
dB
µs
Min Max
15
15
73 146
6.9 13.8
15
15
36
27.6
TBD
TBD
TBD
TBD
50
Unit
ns
ns
ns
MHz
ns
ns
ns
MHz
ns
tMCLK
ns
ns
ns

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Preliminary Technical Data
Parameter
I2C PORT
Start Condition
Stop Condition
Slave Mode
DAC SERIAL PORT
Master Mode
Slave Mode
ADC SERIAL PORT
Master Mode
AUXILIARY INTERFACE
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLH
tCOE
tCOD
tCOH
tCOTS
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tSCS
tDBH
tDBL
fDB
tDLS
tDLH
tDLS
tDDS
tDDH
tABH
tABL
fDB
tALS
tALH
tALS
tABDD
tAXDS
tAXDH
tDXDD
tXBH
tXBL
fXB
tDLS
tDLH
AD1935/AD1936/AD1937/AD1938/AD1939
Comments
CCLK Frequency
CDATA Setup
To CCLK Rising
CDATA Hold
From CCLK Rising
CLATCH Setup
To CCLK Rising
CLATCH Hold
From CCLK Falling
CLATCH High
COUT Enable
From CCLK Falling
COUT Delay
COUT Hold
From CCLK Falling
From CCLK Falling
COUT Three-State
SCL Clock
Frequency
From CCLK Falling
SCL High
SCL Low
Setup Time
Relevant for Repeated Start
Condition
Hold Time
After this period the 1st clock is
generated
Data Setup Time
SCL Rise Time
SCL Fall Time
SDA Rise Time
SDA Fall Time
Setup Time
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
To DBCLK Rising
DLRCLK Hold
DLRCLK Skew
From DBCLK Rising
From DBCLK Falling
DSDATA Setup
To DBCLK Rising
DSDATA Hold
From DBCLK Rising
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
To ABCLK Rising
ALRCLK Hold
From ABCLK Rising
ALRCLK Skew
From ABCLK Falling
ASDATA Delay
From ABCLK Falling
AAUXDATA Setup To AUXBCLK Rising
AAUXDATA Hold From AUXBCLK Rising
DAUXDATA Delay From AUXBCLK Falling
AUXBCLK High
AUXBCLK Low
AUXBCLK
Frequency
AUXLRCLK Setup
To AUXBCLK Rising
AUXLRCLK Hold
From AUXBCLK Rising
Table 8
Min Max
20
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
400
0.6
1.3
0.6
0.6
100
300
300
300
300
0.6
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µS
µS
µS
µS
ns
ns
ns
ns
ns
µS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. PrI | Page 5 of 30