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Preliminary Technical Data
16-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
AD5360/AD5361
FEATURES
16-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V digital interface
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical Line Cards
TEMP_OUT
PEC
MON_IN0
MON_IN1
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
TEMP
SENSOR
CONTROL
REGISTER
8
VOUT0 -
VOUT15
MUX
6
GPIO
REGISTER
2
SERIAL
INTERFACE
AD5360, n = 16
AD5361, n = 14
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
X1A REGISTER
n
MUX
n
n X1B REGISTER
n
1
n
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n X1A REGISTER MUX n
n
n X1B REGISTER
n
1n
M REGISTER
n C REGISTER
n
STATE
MACHINE
n
POWER-ON
RESET
AD5360/
AD5361
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
X1A REGISTER
n
MUX
n
n X1B REGISTER
n
1
n
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
X1A REGISTER
n
MUX
n
n X1B REGISTER
n
1
n
M REGISTER
n C REGISTER
n
14 OFS0 14 OFFSET
REGISTER
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
··
····
DAC 7
14 OFS1 14 OFFSET
REGISTER
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
··
····
DAC 7
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
···
·
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
GROUP 1
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·····
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5360-0001
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
Figure 1.
AD5360/AD5361—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.

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AD5360/AD5361
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Functional Description .................................................................. 12
DAC Architecture—General..................................................... 12
Channel Groups.......................................................................... 12
A/ B Registers Gain/Offset Adjustment .................................. 13
Offset DACS................................................................................ 13
Output Amplifier........................................................................ 14
Transfer Function ....................................................................... 14
Reference Selection .................................................................... 14
Calibration................................................................................... 15
AD5360 Calibration Example................................................... 15
Reset Function ............................................................................ 15
Preliminary Technical Data
Clear Function ............................................................................ 16
BUSY and LDAC Functions...................................................... 16
Monitor Function....................................................................... 17
GPIO Pin ..................................................................................... 17
Power-Down Mode.................................................................... 17
Thermal Monitoring Function ................................................. 17
Toggle Mode................................................................................ 17
Serial Interface ................................................................................ 18
SPI Write Mode .......................................................................... 18
Register Update Rates ................................................................ 18
SPI Readback Mode ................................................................... 19
Channel Addressing And Special Modes................................ 19
Special Function Mode.............................................................. 20
Power Supply Decoupling ......................................................... 22
Power Supply Sequencing ......................................................... 22
Interfacing Examples ................................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
Pr B2.
Pr F
Modified SPI Timing Diagrams
Added Reference Selection and Calibration text
rewrote calibration section
Changed SPI read diagram
Rev. PrF | Page 2 of 25

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Preliminary Technical Data
AD5360/AD5361
GENERAL DESCRIPTION
The AD5360/AD5361 contains 16, 16/14-bit DACs in a single,
56-lead, LFCSP or 52-lead LQFP package. It provides buffered
voltage outputs with a span 4 times the reference voltage. The
gain and offset of each DAC can be independently trimmed to
remove errors. For even greater flexibility, the device is divided
into two groups of 8 DACs, and the output range of each group
can be independently adjusted by an offset DAC.
The AD5360/AD5361 offers guaranteed operation over a wide
supply range with VSS from -4.5 V to -16.5 V and VDD from
+8 V to +16.5 V. The output amplifier headroom requirement is
1.4 V operating with a load current of 1 mA.
Table 1. High Channel Count Bipolar DACs
Model
Resolution Nominal Output
Span
AD5360BCPZ
AD5360BSTZ
AD5361BCPZ
AD5361BSTZ
AD5362BCPZ
AD5362BSTZ
AD5363BCPZ
AD5363BSTZ
AD5370BCPZ
AD5370BSTZ
AD5371BCPZ
AD5371BSTZ
AD5372BCPZ
AD5372BSTZ
AD5373BCPZ
AD5373BSTZ
16 Bits
16 Bits
14 Bits
14 Bits
16 Bits
16 Bits
14 Bits
14 Bits
16 Bits
16 Bits
14 Bits
14 Bits
16 Bits
16 Bits
14 Bits
14 Bits
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
Output
Channels
16
16
16
16
8
8
8
8
40
40
40
40
32
32
32
32
The AD5360/AD5361 has a high-speed 4-wire serial interface,
which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to 50
MHz. All the outputs can be updated simultaneously by taking
the LDAC input low. Each channel has a programmable gain
and an offset adjust register.
Each DAC output is amplified and buffered on-chip with
respect to an external SIGGND input. The DAC outputs can
also be switched to SIGGND via the CLR pin.
Linearity Error
(LSB)
±4
±4
±1
±1
±4
±4
±1
±1
±4
±4
±2
±2
±4
±4
±2
±2
Package Description Package Option
56-Lead LFCSP
52-Lead LQFP
56-Lead LFCSP
52-Lead LQFP
56-Lead LFCSP
52-Lead LQFP
56-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
64-Lead LQFP
100-Ball CSPBGA
80-Lead LQFP
56-Lead LFCSP
64-Lead LQFP
56-Lead LFCSP
64-Lead LQFP
CP-56
ST-52
CP-56
ST-52
CP-56
ST-52
CP-56
ST-52
CP-64
ST-64
BC-100-2
ST-80
CP-56
ST-64
CP-56
ST-64
Rev. PrF | Page 3 of 25

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AD5360/AD5361
Preliminary Technical Data
SPECIFICATIONS
DVCC = 2.3 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; RL = Open
Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.;
Table 2. Performance Specifications
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Offset Error2
Gain Error2
Gain Error of Offset DAC
VOUT Temperature Coefficient
DC Crosstalk1
REFERENCE INPUTS (VREF0, VREF1)1
VREF DC Input Impedance
VREF Input Current
VREF Range4
SIGGND INPUT (SIGGND0, TO SIGGND1)1
DC Input Impedance
Input Range
OUTPUT CHARACTERISTICS1
Output Voltage Range
Nominal Output Voltage Range
Short Circuit Current
Load Current
Capacitive Load
DC Output Impedance
MONITOR PIN (MON_OUT)
Output Impedance
Three State Leakage Current
Continuous Current Limit
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance1
DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC)
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance
B Version1
16
14
±4
±1
±1
±20
±20
100
100
±35
5
0.5
1
60
2/5
55
±0.5
VSS + 1.4
VDD − 1.4
−10 to +10
10
±1
2200
0.5
500
100
2
1.7
2.0
0.8
0.7
±1
10
0.5
DVCC − 0.5
±5
10
Unit Test Conditions/Comments1
Bits
Bits
LSB max
LSB max
LSB max
mV max
mV max
µV max
µV max
mV max
ppm FSR/°C typ
mV max
AD5360
AD5361
AD5360
AD5361
Guaranteed monotonic by design over temperature.
Prior to calibration
Prior to calibration
After calibration
After calibration
Positive or Negative Full Scale. See Offset DACS
section for details
Includes linearity, offset, and gain drift.
Typically 100 µV. Measured channel at mid-scale, full-
scale change on any other channel
MΩ min
nA max
V min/max
Typically 100 MΩ.
Per input. Typically ±30 nA.
±2% for specified operation.
kΩ min
V min/max
Typically 60 kΩ.
V min
V max
V
mA max
mA max
pF max
Ω max
ILOAD = 1 mA.
ILOAD = 1 mA.
Ω typ
nA typ
mA max
V min
V min
V max
V
µA max
pF max
JEDEC compliant.
DVCC = 2.3 V to 3.6 V.
DVCC = 3.6 V to 5.5 V.
DVCC = 2.5 V to 5.5 V.
DVCC = 2.3 V to 2.7 V.
All other digital input pins.
V max
V min
µA max
pF typ
Sinking 200 µA.
Sourcing 200 µA.
SDO only.
Rev. PrF | Page 4 of 25

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Preliminary Technical Data
Parameter
TEMPERATURE SENSOR (TMP_OUT)
Accuracy
Output Voltage at 25 °C
Output Voltage Scale Factor
Output Voltage Range
Output Load Current
Power On Time
POWER REQUIREMENTS
DVCC
VDD
VSS
Power Supply Sensitivity1
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
DICC
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature
B Version1
±1
±5
1.5
5
0/3
200
10
2.3/5.5
8/16.5
−4.5/−16.5
−75
−75
−90
2
7
7
173
130
Unit
°C
°C max
V typ
mV/°C typ
V min/max
µA max
ms typ
V min/max
V min/max
V min/max
dB typ
dB typ
dB typ
mA max
mA max
mA max
mW
°C max
1 Temperature range for B Version: -40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJ represents the package thermal impedance.
4. Specifications are guaranteed for a 5V reference only.
AD5360/AD5361
Test Conditions/Comments1
@25 °C
-40 °C < T < +85°C
Current source only.
To within ±5 °C
VCC = 5.5 V, VIH = VCC, VIL = GND.
Outputs unloaded.
Outputs unloaded.
VSS = -12 V, VDD = +12 V, DVCC = 2.5 V
TJ = TA + PTOTAL × θJ3
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; RL = 10 kΩ to GND; CL = 200 pF to GND;
Gain (m), Offset(c) and DAC Offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
B Version1,2 Unit
Test Conditions/Comments
TBD µs typ
Full-scale change
30
µs max
DAC latch contents alternately loaded with all 0s and all 1s.
1 V/µs typ
20 nV-s typ
10 mV max
100 dB typ
40
nV-s typ
Between DACs inside a group.
10
nV-s typ
Between DACs from different groups.
0.1 nV-s typ
1
nV-s typ
Effect of input bus activity on DAC output under test.
250 nV/(Hz)1/2 typ VREF = 0 V.
1 Temperature range for B Version: -40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
Rev. PrF | Page 5 of 25