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40-Channel, 3 V/5 V, Single-Supply,
Serial, 14-Bit Voltage Output DAC
AD5384
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead CSPBGA (10 mm × 10 mm)
User Interfaces:
Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible,
featuring data readback)
I2C-®compatible
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
PD
SYNC/AD 0
DCEN/AD 1
DVDD (×3)
DGND (×4)
FUNCTIONAL BLOCK DIAGRAM
AVDD (×5)
AGND (×5) DAC GND (×5)
REFGND
REFOUT/REFIN SIGNAL GND (×5)
AD5384
1.25V/2.5V
REFERENCE
SDO
DIN/SDA
SCLK/SCL
SPI/I2C
INTERFACE
CONTROL
LOGIC
STATE
MACHINE
+
CONTROL
LOGIC
RESET
BUSY
CLR
POWER-ON
RESET
VOUT0……VOUT38
39-TO-1
MUX
14 INPUT 14
REG 0
14 m REG 0
14 c REG 0
14 INPUT 14
REG 1
14 m REG 1
14 c REG 1
14 INPUT 14
REG 6
14 m REG 6
14 c REG 6
14 INPUT 14
REG 7
14 m REG 7
14 c REG 7
14
DAC 14
REG 0
DAC 0
14
DAC 14
REG 1
DAC 1
14
DAC 14
REG 6
DAC 6
14
DAC 14
REG 7
DAC 7
×5
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT38
VOUT39/MON_OUT
LDAC
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

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AD5384
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
AD5384-5 Specifications ............................................................. 4
AC Characteristics........................................................................ 6
AD5384-3 Specifications ............................................................. 7
AC Characteristics........................................................................ 9
Timing Characteristics................................................................... 10
Serial Interface ............................................................................ 10
I2C Serial Interface...................................................................... 12
Absolute Maximum Ratings.......................................................... 13
Pin Configuration and Function Descriptions........................... 14
Terminology .................................................................................... 17
Typical Performance Characteristics ........................................... 18
Functional Description .................................................................. 21
DAC Architecture—General..................................................... 21
Data Decoding ............................................................................ 21
On-Chip Special Function Registers (SFR) ............................ 22
SFR Commands .......................................................................... 22
Hardware Functions....................................................................... 25
REVISION HISTORY
10/04—Changed from Rev. 0 to Rev. A
Changes to Table 19........................................................................ 24
Changes to Ordering Guide .......................................................... 35
7/04—Revision 0: Initial Version
Reset Function ............................................................................ 25
Asynchronous Clear Function.................................................. 25
BUSY and LDAC Functions...................................................... 25
Power-On Reset.......................................................................... 25
Power-Down ............................................................................... 25
Interfaces.......................................................................................... 26
DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ 26
I2C Serial Interface ..................................................................... 28
Microprocessor Interfacing....................................................... 31
Application Information................................................................ 32
Power Supply Decoupling ......................................................... 32
Monitor Function....................................................................... 32
Toggle Mode Function............................................................... 32
Thermal Monitor Function....................................................... 33
AD5384 in a MEMS-Based Optical Switch ............................ 33
Optical Attenuators.................................................................... 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Rev. A | Page 2 of 36

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GENERAL DESCRIPTION
The AD5384 is a complete single-supply, 40-channel, 14-bit
DAC available in a 100-lead CSPBGA package. All 40 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C
reference, an on-chip channel monitor function that multiplexes
the analog outputs to a common MON_OUT pin for external
monitoring, and an output amplifier boost mode that allows the
amplifier slew rate to be optimized. The AD5384 contains a
serial interface compatible with SPI, QSPI, MICROWIRE, and
AD5384
DSP interface standards with interface speeds in excess of
30 MHz and an I2C-compatible interface supporting 400 kHz
data transfer rate. An input register followed by a DAC register
provides double buffering, allowing the DAC outputs to be
updated independently or simultaneously. using the LDAC
input. Each channel has a programmable gain and offset adjust
register letting the user fully calibrate any DAC channel. Power
consumption is typically 0.25 mA/channel with boost mode off.
Table 1. Complete Family of High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Model
Resolution AVDD Range Output Channels Linearity Error (LSB) Package Description
AD5380BST-5 14 Bits
4.5 V to 5.5 V 40
±4
100-Lead LQFP
AD5380BST-3 14 Bits
2.7 V to 3.6 V 40
±4
100-Lead LQFP
AD5381BST-5 12 Bits
4.5 V to 5.5 V 40
±1
100-Lead LQFP
AD5381BST-3 12 Bits
2.7 V to 3.6 V 40
±1
100-Lead LQFP
AD5384BBC-5 14 Bits
4.5 V to 5.5 V 40
±4
100-Lead CSPBGA
AD5384BBC-3 14 Bits
2.7 V to 3.6 V 40
±4
100-Lead CSPBGA
AD5382BST-5 14 Bits
4.5 V to 5.5 V 32
±4
100-Lead LQFP
AD5382BST-3 14 Bits
2.7 V to 3.6 V 32
±4
100-Lead LQFP
AD5383BST-5 12 Bits
4.5 V to 5.5 V 32
±1
100-Lead LQFP
AD5383BST-3 12 Bits
2.7 V to 3.6 V 32
±1
100-Lead LQFP
AD5390BST-5 14 Bits
4.5 V to 5.5 V 16
±3
52-Lead LQFP
AD5390BCP-5 14 Bits
4.5 V to 5.5 V 16
±3
64-Lead LFCSP
AD5390BST-3 14 Bits
2.7 V to 3.6 V 16
±4
52-Lead LQFP
AD5390BCP-3 14 Bits
2.7 V to 3.6 V 16
±4
64-Lead LFCSP
AD5391BST-5 12 Bits
4.5 V to 5.5 V 16
±1
52-Lead LQFP
AD5391BCP-5 12 Bits
4.5 V to 5.5 V 16
±1
64-Lead LFCSP
AD5391BST-3 12 Bits
2.7 V to 3.6 V 16
±1
52-Lead LQFP
AD5391BCP-3 12 Bits
2.7 V to 3.6 V 16
±1
64-Lead LFCSP
AD5392BST-5 14 Bits
4.5 V to 5.5 V 8
±3
52-Lead LQFP
AD5392BCP-5 14 Bits
4.5 V to 5.5 V 8
±3
64-Lead LFCSP
AD5392BST-3 14 Bits
2.7 V to 3.6 V 8
±4
52-Lead LQFP
AD5392BCP-3 14 Bits
2.7 V to 3.6 V 8
±4
64-Lead LFCSP
Package Option
ST-100
ST-100
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
Table 2. 40-Channel, Bipolar Voltage Output DAC
Model
Resolution Analog Supplies Output Channels
AD5379ABC 14 Bits
±11.4 V to ±16.5 V 40
Linearity Error (LSB) Package
±3 108-Lead CSPBGA
Package Option
BC-108
Rev. A | Page 3 of 36

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AD5384
SPECIFICATIONS
AD5384-5 SPECIFICATIONS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter
ACCURACY
Resolution
Relative Accuracy2 (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Offset Error
Offset Error TC
Gain Error
Gain Temperature Coefficient3
DC Crosstalk3
REFERENCE INPUT/OUTPUT
Reference Input3
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output4
Output Voltage
Reference TC
OUTPUT CHARACTERISTICS3
Output Voltage Range2
Short-Circuit Current
Load Current
Capacitive Load Stability
RL = ∞
RL = 5 kΩ
DC Output Impedance
MONITOR PIN
Output Impedance
Three-State Leakage Current
LOGIC INPUTS (EXCEPT SDA/SCL)3
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
LOGIC INPUTS (SDA, SCL ONLY)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
AD5384-51 Unit
14
±4
–1/+2
4
±4
±5
±0.024
±0.06
2
0.5
Bits
LSB max
LSB max
mV max
mV max
µV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
LSB max
Test Conditions/Comments
±1 LSB typical
Guaranteed monotonic by design over temperature
Measured at code 32 in the linear region
At 25°C
TMIN to TMAX
2.5
1
±1
1 to VDD/2
V
MΩ min
µA max
V min/max
2.495/2.505
1.22/1.28
±10
±15
V min/max
V min/max
ppm/°C max
ppm/°C max
0/AVDD
40
±1
V min/max
mA max
mA max
200
1000
0.5
pF max
pF max
Ω max
500 Ω typ
100 nA typ
2 V min
0.8 V max
±10 µA max
10 pF max
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
8
50
V min
V max
µA max
V min
pF typ
ns max
±1% for specified performance, AVDD = 2 × REFIN + 50 mV
Typically 100 MΩ
Typically ±30 nA
Enabled via CR10 in the AD5384 control register, CR12,
selects the output voltage.
At ambient; CR12 = 1; optimized for 2.5 V operation
CR12 = 0
Temperature range: +25°C to +85°C
Temperature range: −40°C to +85°C
DVDD = 2.7 V to 5.5 V
Total for all pins. TA = TMIN to TMAX
SMBus-compatible at DVDD < 3.6 V
SMBus-compatible at DVDD < 3.6 V
Input filtering suppresses noise spikes of less than 50 ns
Rev. A | Page 4 of 36

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AD5384
Parameter
LOGIC OUTPUTS (BUSY, SDO)3
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)3
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity3
∆Midscale/∆ΑVDD
AIDD
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
AD5384-51 Unit
Test Conditions/Comments
0.4
DVDD – 1
0.4
DVDD – 0.5
±1
5
V max
V min
V max
V min
µA max
pF typ
DVDD = 5 V ± 10%, sinking 200 µA
DVDD = 5 V ± 10%, sourcing 200 µA
DVDD = 2.7 V to 3.6 V, sinking 200 µA
DVDD = 2.7 V to 3.6 V, sourcing 200 µA
SDO only
SDO only
0.4 V max
0.6 V max
±1 µA max
8 pF typ
ISINK = 3 mA
ISINK = 6 mA
4.5/5.5
2.7/5.5
V min/max
V min/max
–85
0.375
0.475
1
2
20
80
dB typ
mA/channel max
mA/channel max
mA max
µA max
µA max
mW max
Outputs unloaded, boost off; 0.25 mA/channel typ
Outputs unloaded, boost on; 0.32 5mA/channel typ
VIH = DVDD, VIL = DGND
Typically 200 nA
Typically 3 µA
Outputs unloaded, boost off, AVDD = DVDD = 5 V
1 AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.
2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3 Guaranteed by characterization, not production tested.
4 Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to
degraded accuracy specifications.
Rev. A | Page 5 of 36