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Data Sheet
8-/10-/12-/14-Bit, 175 MSPS TxDAC
Digital-to-Analog Converters
AD9704/AD9705/AD9706/AD9707
FEATURES
175 MSPS update rate
Low power member of pin-compatible
TxDAC product family
Low power dissipation
12 mW at 80 MSPS, 1.8 V
50 mW at 175 MSPS, 3.3 V
Wide supply voltage: 1.7 V to 3.6 V
SFDR to Nyquist
AD9707: 84 dBc at 5 MHz output
AD9707: 83 dBc at 10 MHz output
AD9707: 75 dBc at 20 MHz output
Adjustable full-scale current outputs: 1 mA to 5 mA
On-chip 1.0 V reference
CMOS-compatible digital interface
Common-mode output: adjustable 0 V to 1.2 V
Power-down mode <2 mW at 3.3 V (SPI controllable)
Self-calibration
Compact 32-lead LFCSP, RoHS compliant package
GENERAL DESCRIPTION
The AD9704/AD9705/AD9706/AD9707 are the fourth-generation
family in the TxDAC series of high performance, CMOS digital-to-
analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit
resolution family is optimized for low power operation, while
maintaining excellent dynamic performance. The AD9704/
AD9705/AD9706/AD9707 family is pin-compatible with the
AD9748/AD9740/AD9742/AD9744 family of TxDAC converters
and is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface, LFCSP package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The AD9704/AD9705/AD9706/AD9707
offers exceptional ac and dc performance, while supporting
update rates up to 175 MSPS.
The flexible power supply operating range of 1.7 V to 3.6 V and low
power dissipation of the AD9704/AD9705/AD9706/AD9707 parts
make them well suited for portable and low power applications.
Power dissipation of the AD9704/AD9705/AD9706/AD9707 can
be reduced to 15 mW, with a small trade-off in performance, by
lowering the full-scale current output. In addition, a power-down
mode reduces the standby power dissipation to approximately
2.2 mW.
The AD9704/AD9705/AD9706/AD9707 has an optional serial
peripheral interface (SPI®) that provides a higher level of program-
mability to enhance performance of the DAC. An adjustable
output, common-mode feature allows for easy interfacing to other
components that require common modes from 0 V to 1.2 V.
Edge-triggered input latches and a 1.0 V temperature-compensated
band gap reference have been integrated to provide a complete,
monolithic DAC solution. The digital inputs support 1.8 V and
3.3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. Pin Compatible. The AD9704/AD9705/AD9706/AD9707
line of TxDAC® converters is pin-compatible with the
AD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP
package).
2. Low Power. Complete CMOS DAC operates on a single
supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V)
and 12 mW (1.8 V). The DAC full-scale current can be
reduced for lower power operation. Sleep and power-down
modes are provided for low power idle periods.
3. Self-Calibration. Self-calibration enables true 14-bit INL
and DNL performance in the AD9707.
4. Twos Complement/Binary Data Coding Support. Data
input supports twos complement or straight binary data
coding.
5. Flexible Clock Input. A selectable high speed, single-ended,
and differential CMOS clock input supports 175 MSPS
conversion rate.
6. Device Configuration. Device can be configured through
pin strapping, and SPI control offers a higher level of
programmability.
7. Easy Interfacing to Other Components. Adjustable
common-mode output allows for easy interfacing to other
signal chain components that accept common-mode levels
from 0 V to 1.2 V.
8. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/
AD9707 include a 1.0 V temperature-compensated band
gap voltage reference.
9. Industry-Standard 32-Lead LFCSP Package.
Rev. D
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Tel: 781.329.4700 ©2006–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9704/AD9705/AD9706/AD9707
TABLE OF CONTENTS
Features .............................................................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Functional Block Diagram .............................................................. 4 
Specifications..................................................................................... 5 
DC Specifications (3.3 V)............................................................ 5 
Dynamic Specifications (3.3 V).................................................. 6 
Digital Specifications (3.3 V) ...................................................... 7 
DC Specifications (1.8 V)............................................................ 8 
Dynamic Specifications (1.8 V).................................................. 9 
Digital Specifications (1.8 V) .................................................... 10 
Timing Diagram ......................................................................... 10 
Absolute Maximum Ratings.......................................................... 11 
Thermal Characteristics ............................................................ 11 
ESD Caution................................................................................ 11 
Pin Configurations and Function Descriptions ......................... 12 
AD9707 ........................................................................................ 12 
AD9706 ........................................................................................ 13 
AD9705 ........................................................................................ 14 
AD9704 ........................................................................................ 15 
Typical Performance Characteristics ........................................... 16 
AD9707......................................................................................... 16 
AD9704, AD9705 and AD9706.................................................. 23 
Data Sheet
Terminology .................................................................................... 29 
Theory of Operation ...................................................................... 30 
Serial Peripheral Interface......................................................... 30 
SPI Register Map ........................................................................ 32 
SPI Register Descriptions.......................................................... 33 
Reference Operation .................................................................. 34 
Reference Control Amplifier .................................................... 34 
DAC Transfer Function ............................................................. 35 
Analog Outputs .......................................................................... 35 
Adjustable Output Common Mode......................................... 36 
Digital Inputs .............................................................................. 36 
Clock Input.................................................................................. 36 
DAC Timing................................................................................ 36 
Power Dissipation....................................................................... 37 
Self-Calibration........................................................................... 38 
Applications Information .............................................................. 40 
Output Configurations .............................................................. 40 
Differential Coupling Using a Transformer ............................... 40 
Single-Ended Buffered Output Using an Op Amp ................ 40 
Differential Buffered Output Using an Op Amp ................... 41 
Evaluation Board ........................................................................ 41 
Outline Dimensions ....................................................................... 42 
Ordering Guide .......................................................................... 42 
REVISION HISTORY
11/2017—Rev. C to Rev. D
Changed CP-32-7 to CP-32-2 ...................................... Throughout
Updated Outline Dimensions ....................................................... 42
Changes to Ordering Guide .......................................................... 42
9/2017—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Table 9.......................................................................... 12
Changes to Table 10........................................................................ 13
Changes to Table 11........................................................................ 14
Changes to Table 12........................................................................ 15
Changes to Reference Operation Section.................................... 34
Updated Outline Dimensions ....................................................... 42
Changes to Ordering Guide .......................................................... 42
10/2011—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 5
Changes to Table 2.............................................................................6
Changes to Table 4.............................................................................8
Changes to Table 5.............................................................................9
Changes to Figure 3 and Table 9................................................... 12
Changes to Figure 4 and Table 10................................................. 13
Changes to Figure 5 and Table 11................................................. 14
Changes to Figure 6 and Table 12................................................. 15
Changes to Figure 15 and Figure 16............................................. 17
Moved Figure 41 to Figure 24 Position........................................ 18
Moved Figure 42 to Figure 25 Position and Moved Figure 43 to
Figure 26 Position........................................................................... 19
Changes to Figure 27...................................................................... 20
Changes to Figure 33 to Figure 35................................................ 21
Moved Figure 24 to Figure 41 Position........................................ 22
Moved Figure 25 to Figure 43 Position and Moved Figure 26 to
Figure 44 Position........................................................................... 23
Changes to Figure 44...................................................................... 23
Changes to Figure 57...................................................................... 26
Rev. D | Page 2 of 42

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Data Sheet
Changes to Figure 44 ......................................................................23
Changes to Figure 57 ......................................................................26
Changes to Figure 70 ......................................................................29
Changes to Serial Peripheral Interface Section ...........................30
Changes to Table 15 ........................................................................32
Deleted Table 23; Renumbered Sequentially ...............................33
Changes to Reference Operation Section and Reference Control
Amplifier Section ............................................................................34
Changes to Adjustable Output Common Mode Section and
DAC Timing Section.......................................................................36
Added the Deskew Mode Section .................................................36
Deleted Figure 80; Renumbered Sequentially .............................36
Changed Sleep and Power-Down Operation (Pin Mode) Section
to Sleep Operation (Pin Mode) Section .......................................38
Changes to Sleep Operation (Pin Mode) Section .......................38
Changes to Self-Calibration Section.............................................39
Changes to Evaluation Board Section ..........................................41
Added Exposed Pad Notation to Outline Dimensions ..............42
Changes to Ordering Guide...........................................................42
Deleted Evaluation Board Schematics Section............................43
Deleted Figure 92 to Figure 102 ....................................................43
AD9704/AD9705/AD9706/AD9707
4/2007—Rev. 0 to Rev. A
Changes to Features List...................................................................1
Changes to Product Highlights .......................................................1
Changes to General Description .....................................................3
Changes to Table 3 ............................................................................6
Changes to Table 4 ............................................................................7
Changes to Table 6 ............................................................................9
Changes to Figure 17 and Figure 18 .............................................16
Deleted Figure 29, Renumbered Sequentially .............................19
Changes to Figure 44 ......................................................................22
Changes to Figure 57 Caption .......................................................25
Changes to Figure 73, Figure 75, and Figure 77..........................31
Changes to Table 16 ........................................................................32
Replaced Single-Ended Buffered Output Using an Op
Amp Section ....................................................................................40
Changes to Figure 91 ......................................................................41
Changes to Figure 93 ......................................................................44
Changes to Figure 96 ......................................................................47
7/2006—Revision 0: Initial Version
Rev. D | Page 3 of 42

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AD9704/AD9705/AD9706/AD9707
FUNCTIONAL BLOCK DIAGRAM
1.7V TO 3.6V
0.1µF
RSET
1.7V
TO
3.6V
CLK+
CLK–
1.7V TO
3.6V
1.0V REF
REFIO
FS ADJ
AVDD
CURRENT
SOURCE
ARRAY
ACOM
AD9707
OTCM
CLKVDD
CLKCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
DVDD
DCOM
LATCHES
SPI
PIN/SPI/RESET
MODE/SDIO
CMODE/SCLK
DIGITAL INPUTS (DB13 TO DB0) SLEEP/CSB
Figure 1.
Data Sheet
Rev. D | Page 4 of 42

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Data Sheet
AD9704/AD9705/AD9706/AD9707
SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY1
Integral Nonlinearity (INL)
Precalibration
Integral Nonlinearity (INL)
Postcalibration
Differential Nonlinearity
(DNL) Precalibration
Differential Nonlinearity
(DNL) Postcalibration
ANALOG OUTPUT
Offset Error
Gain Error (With External
Reference
Gain Error (With Internal
Reference)
Full-Scale Output Current2
Output Compliance Range
(From OTCM to
IOUTA/IOUTB)
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
(Reference Powered Up)
Reference Input Resistance
(Reference Powered Down)
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal
Reference)
Gain Drift (With Internal
Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltage
AVDD
DVDD
CLKVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Clock Supply Current (ICLKVDD)4
Power Dissipation4
Supply Current Sleep Mode
(IAVDD)
AD9707
Min Typ Max
14
±1.4 ±6.0
±0.9
±1.2 ±4.4
±0.4
−0.03 0
−2.7 −0.1
−2.7 −0.1
12
−0.8
+0.03
+2.7
+2.7
5
+0.8
200
5
0.98 1.025 1.08
100
0.1
10
1
1.25
0
±29
±40
±25
3.3 3.6
3.3 3.6
3.3 3.6
5.2 6.7
5.9 6.6
4.1 4.7
50.2 57
0.37 0.4
AD9706
Min Typ Max
12
±0.41 ±1.48
±0.30
±0.35 ±1.17
±0.13
−0.03 0
−2.7 −0.1
−2.7 −0.1
12
−0.8
+0.03
+2.7
+2.7
5
+0.8
200
5
0.98 1.025 1.08
100
0.1
10
1
1.25
0
±29
±40
±25
3.3 3.6
3.3 3.6
3.3 3.6
5.2 6.7
5.4 6.6
4.1 4.7
48.5 57
0.37 0.4
AD9705
Min Typ Max
10
±0.10 ±0.36
±0.10
±0.09 ±0.31
±0.03
−0.03 0
−2.7 −0.1
−2.7 −0.1
12
−0.8
+0.03
+2.7
+2.7
5
+0.8
200
5
0.98 1.025 1.08
100
0.1
10
1
1.25
0
±29
±40
±25
3.3 3.6
3.3 3.6
3.3 3.6
5.1 6.7
5.0 6.6
4.1 4.7
46.9 57
0.37 0.4
AD9704
Min Typ Max
8
±0.03 ±0.09
±0.02 ±0.08
−0.03 0
+0.03
−2.7 −0.1 +2.7
−2.7 −0.1 +2.7
12
−0.8
5
+0.8
200
5
0.98 1.025 1.08
100
0.1
10
1
1.25
0
±29
±40
±25
3.3 3.6
3.3 3.6
3.3 3.6
5.1 6.7
4.6 6.6
4.1 4.7
45.5 57
0.37 0.4
Unit
Bits
LSB
LSB
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
MΩ
pF
V
nA
V
kΩ
MΩ
ppm of
FSR/°C
ppm of
FSR/°C
ppm of
FSR/°C
ppm/°C
V
V
V
mA
mA
mA
mW
mA
Rev. D | Page 5 of 42