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CCD Signal Processor with Vertical Driver
and Precision Timing ™ Generator
AD9925
FEATURES
Integrated 10-channel V-driver
Register-compatible with the AD9991 and AD9995
3-field (6-phase) vertical clock support
2 additional vertical outputs for advanced CCDs
Complete on-chip timing generator
Precision Timing core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit 36 MHz ADC
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSPBGA package with 0.65 mm pitch
APPLICATIONS
Digital still cameras
Digital video camcorders
CCD camera modules
GENERAL DESCRIPTION
The AD9925 is a complete 36 MHz front end solution for digi-
tal still camera and other CCD imaging applications. Based on
the AD9995 product, the AD9925 includes the analog front end
and a fully programmable timing generator (AFETG), combined
with a 10-channel vertical driver (V-driver). A Precision Timing
core allows adjustment of high speed clocks with approximately
600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 10 channels for use with
3-field (6-phase) CCDs. Two additional vertical outputs can be
used with CCDs that contain advanced video readout modes.
Voltage levels of up to +15 V and −8 V are supported.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks,
sensor gate pulses, substrate clock, and substrate bias control.
The internal registers are programmed using a 3-wire serial
interface.
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-
fied over an operating temperature range of −25°C to +85°C.
CCDIN
RG
H1 TO H4
V1, V2
V3A, V3B
V4, V6
V5A, V5B
V7, V8
SUBCK
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
0dB, –2dB, –4dB
CDS
6dB TO 42dB
VGA
VREF
12-BIT
ADC
CLAMP
INTERNAL CLOCKS
AD9925
12
DOUT
DCLK
HORIZONTAL
4 DRIVERS
XV1 TO XV8
8
10 XSG1 TO XSG6
V-DRIVER
6
VERTICAL
TIMING
CONTROL
SUBCK
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
MSHUT
STROBE
SL
SDI
SCK
RSTB
VSUB
HD VD SYNC CLI CLO
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

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AD9925
TABLE OF CONTENTS
Specifications..................................................................................... 3
Digital Specifications........................................................................ 4
Vertical Driver Specifications ......................................................... 5
Analog Specifications....................................................................... 6
Timing Specifications....................................................................... 7
Absolute Maximum Ratings............................................................ 8
Package Thermal Characteristics ............................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Equivalent Circuits ......................................................................... 12
Typical Performance Characteristics ........................................... 13
System Overview ........................................................................ 14
Precision Timing High Speed Timing Generation.................. 15
Horizontal Clamping and Blanking......................................... 18
Horizontal Timing Sequence Example.................................... 21
Vertical Timing Generation...................................................... 22
Vertical Timing Example........................................................... 34
Shutter Timing Control ............................................................. 36
Example of Exposure and Readout of Interlaced Frame........... 41
FG_TRIG Operation.................................................................. 43
Analog Front End Description and Operation ...................... 45
Vertical Driver Signal Configuration ...................................... 47
Power-Up and Synchronization ............................................... 51
Standby Mode Operation .......................................................... 55
Circuit Layout Information....................................................... 57
Serial Interface Timing .............................................................. 59
Complete Listing for Register Bank 1.......................................... 62
Complete Listing for Register Bank 2.......................................... 66
Complete Listing for Register Bank 3.......................................... 87
Outline Dimensions ....................................................................... 94
Ordering Guide .......................................................................... 94
REVISION HISTORY
10/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Specifications ........................................................................................3
Added Stress Disclaimer..........................................................................................8
Changes to Figure 12................................................................................................13
Changes to Figure 22................................................................................................18
Changes to Figure 55................................................................................................45
Change to DC Restore Section ...............................................................................45
Change to Correlated Double Sampler Section....................................................45
Change to ADC Section...........................................................................................46
Change to Digital Data Outputs Section ...............................................................46
Added Paragraph to Digital Data Outputs Section..............................................46
Changes to Table 34..................................................................................................55
Change to Circuit Layout Information Section....................................................57
Changes to Register Address Bank 1, Bank 2, and Bank 3 Section ...................60
Changes to Table 40..................................................................................................63
Change to Table 46 ...................................................................................................65
Changes to Tables 47–56, 58–73.............................................................................66
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 96

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AD9925
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGES
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1 to H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
V-DRIVER SUPPLY VOLTAGES
VDVDD (V-Driver Input Logic Supply)
VH1, VH2 (V-Driver High Supply for 3-Level Outputs)
VM1, VM2 (V-Driver Mid Supply for 3-Level and 2-Level Outputs)
VL1, VL2 (V-Driver Low Supply for 3-Level and 2-Level Outputs)
POWER DISSIPATION—AFETG Section Only (see Figure 9 for Power Curves)
36 MHz, 3.0 V Supply, 100 pF Load on Each H1 to H4 Output, 20 pF RG Load
Standby 1 Mode
Standby 2 Mode
Standby 3 Mode
Power from HVDD Only1
Power from RGVDD Only
Power from AVDD Only
Power from TCVDD Only
Power from DVDD Only
Power from DRVDD Only
POWER DISSIPATION—V-Driver Section Only (VDVDD, VH, VL)
Normal Operation (VH = 15.0 V, VL = −7.5 V)2
Standby 1 Mode2
Standby 2 Mode2
Standby 3 Mode2
MAXIMUM CLOCK RATE (CLI)
Min
–25
–65
2.7
2.7
2.7
2.7
2.7
2.7
2.7
10.5
–1.0
–10.0
36
Typ
3.0
3.0
3.0
3.0
3.0
3.0
3.0
15.0
0.0
–7.5
370
10
10
1
130
10
105
42
57
26
60
70
70
110
Max
+85
+150
3.6
3.6
3.6
3.6
3.6
3.6
3.6
16.0
+3.0
–6.0
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
MHz
1 The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD.
Reducing the H-loading and/or using a lower HVDD supply will reduce the power dissipation. CLOAD is the total capacitance seen by all H-outputs.
2 The power dissipated by the V-driver circuitry depends on the logic states of the inputs as well as actual CCD operation; default dc values are used for each measure-
ment, in each mode of operation. Load conditions are described in the Vertical Driver Specifications section.
Rev. A | Page 3 of 96

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AD9925
DIGITAL SPECIFICATIONS
RGVDD = HVDD = DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (Powered by DVDD, DRVDD)
High Level Output Voltage at IOH = 2 mA
Low Level Output Voltage at IOL = 2 mA
RG and H-DRIVER OUTPUTS (Powered by HVDD, RGVDD)
High Level Output Voltage at Maximum Current
Low Level Output Voltage at Maximum Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (for Each Output)
Symbol
VIH
VIL
IIH
IIL
CIN
VOH
VOL
Min Typ
2.1
10
10
10
VDD – 0.5
VDD – 0.5
30
100
Max Unit
V
0.6 V
µA
µA
pF
V
0.5 V
V
0.5 V
mA
pF
Rev. A | Page 4 of 96

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VERTICAL DRIVER SPECIFICATIONS
VDVDD = 3.3 V, VH = 15 V, VM = 0 V, VL = −7.5 V, CL shown in load model, 25°C.
Table 3.
Parameter
3-LEVEL OUTPUTS (V1, V2, V3A, V3B, V5A, V5B)
(Simplified Load Conditions, 6000 pF to Ground)
Delay Time, VL to VM and VM to VH
Delay Time, VM to VL and VH to VM
Rise Time, VL to VM and VM to VH
Fall Time, VM to VL and VH to VM
Output Currents
At −7.25 V
At −0.25 V
At +0.25 V
At +14.75 V
2-LEVEL OUTPUTS (V4, V6, V7, V8)
(Simplified Load Conditions, 6000 pF to Ground)
Delay Time, VL to VM
Delay Time, VM to VL
Rise Time, VL to VM
Fall Time, VM to VL
Output Currents
At −7.25 V
At −0.25 V
SUBCK OUTPUT
(Simplified Load Conditions, 1000 pF to Ground)
Delay Time, VL to VH
Delay Time, VH to VL
Rise Time, VL to VH
Fall Time, VH to VL
Output Currents
At −7.25 V
At +14.75 V
SERIAL VERTICAL CLOCK RESISTANCE
GND VERTICAL CLOCK RESISTANCE
Symbol
tPLM, tPMH
tPML, tPHM
tRLM, tRMH
tFML, tFHM
tPLM
tPML
tRLM
tFML
tPLH
tPHL
tRLH
tFHL
Min
Typ
10.0
−5.0
5.0
−7.2
10.0
−5.0
5.4
−4.0
30
10
V-DRIVER
INPUT
50%
50%
V-DRIVER
OUTPUT
tRLM, tRMH, tRLH
90%
tPLM, tPMH, tPLH
10%
tPML, tPHM, tPHL
90%
tFML, tFHM, tFHL
10%
Figure 2. Definition of V-Driver Timing Specifications
Max
100
200
500
500
100
200
500
500
100
200
200
200
AD9925
Unit
ns
ns
ns
ns
mA
mA
mA
mA
ns
ns
ns
ns
mA
mA
ns
ns
ns
ns
mA
mA
Rev. A | Page 5 of 96