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14-Bit CCD Signal Processor with V-Driver
and Precision TimingTM Generator
AD9927
FEATURES
Integrated 18-channel V-driver
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock signals
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 40 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
128-lead CSP_BGA package, 9 mm × 9 mm, 0.65 mm pitch
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9927 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with A/D conversion, combined with a full-function
programmable timing generator and 18-channel vertical driver
(V-driver). The timing generator is capable of supporting up to
24 vertical clock signals to control advanced CCDs. The on-
chip V-driver supports up to 18 channels for use with 5-field
CCDs. A Precision Timing core allows adjustment of high speed
clocks with approximately 400 ps resolution at 40 MHz
operation. The AD9927 also contains eight general-purpose
outputs, which can be used for shutter and system functions.
The analog front end includes black level clamping, CDS, VGA,
and a 14-bit ADC. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
The AD9927 is specified over an operating temperature range
of –25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
–3dB, 0dB, +3dB, +6dB
CCDIN
CDS
VGA
VREF
14-BIT
ADC
14
3V INPUT
1.8V OUTPUT
LDO
REG
6dB TO 42dB
CLAMP
1.8V INPUT
3V OUTPUT
RG
HL
H1 TO H8
V1A-V6 (3-LEVEL)
V7-V15 (2-LEVEL)
SUBCK
CHARGE
PUMP
HORIZONTAL
8 DRIVERS
18 XV1 TO XV24
VERTICAL
DRIVER
24
VERTICAL
TIMING
CONTROL
XSUBCK 8
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
AD9927
INTERNAL
REGISTERS
DOUT
SL
SCK
SDATA
XSUBCNT
GP01 TO GP08
HD VD SYNC CLI CLO
Figure 1.
RSTB
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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AD9927
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
Digital Specifications ................................................................... 4
Analog Specifications................................................................... 5
Timing Specifications .................................................................. 6
Vertical Driver Specifications ..................................................... 7
Absolute Maximum Ratings............................................................ 8
Package Thermal Characteristics ............................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 12
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 14
System Overview ............................................................................ 15
High Speed Precision Timing Core........................................... 16
Horizontal Clamping and Blanking......................................... 20
Horizontal Timing Sequence Example.................................... 26
Vertical Timing Generation ...................................................... 28
Vertical Sequences (VSEQ) ....................................................... 31
REVISION HISTORY
1/06—Revision 0: Initial Version
Internal Vertical Driver Connections...................................... 45
Vertical Timing Example........................................................... 53
Shutter Timing Control ............................................................. 55
Substrate Clock Operation (SUBCK) ...................................... 55
Field Counters............................................................................. 58
General-Purpose Outputs (GPOS) .......................................... 59
GP Look-Up Tables (LUT)........................................................ 63
Complete Exposure/Readout Operation
Using Primary Counter and GPO Signals .............................. 64
Manual Shutter Operation Using Enhanced SYNC Modes .... 66
Analog Front-End Description and Operation...................... 70
Power-Up Sequence for Master Mode..................................... 72
Standby Mode Operation .......................................................... 76
CLI Frequency Change.............................................................. 76
Circuit Layout Information........................................................... 78
Serial Interface Timing .............................................................. 82
Layout of Internal Registers ...................................................... 83
Updating New Register Values ................................................. 84
Complete Register Listing ............................................................. 85
Outline Dimensions ....................................................................... 99
Ordering Guide .......................................................................... 99
Rev. 0 | Page 2 of 100

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AD9927
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE INPUTS
AVDD (AFE Analog Supply)
TCVDD (Timing Core Supply)
CLIVDD (CLI Input Supply)
RGVDD (RG, HL Driver)
HVDD (H1 to H8 Drivers)
DVDD (Digital Logic)
DRVDD (Parallel Data Output Drivers)
IOVDD (Digital I/O)
XVVDD (Vertical Output Drivers)
CP1P8 (CP Supply Input)
LDOIN (LDO Supply Input)
V-DRIVER POWER SUPPLY VOLTAGES
VDD1, VDD2 (V-Driver Logic)
VH1, VH2 (V-Driver High Supply)
VL1, VL2 (V-Driver Low Supply)
VM1, VM2 (V-Driver Mid Supply)
VLL (SUBCK Low Supply)
VMM (SUBCK Mid Supply)
POWER SUPPLY CURRENTS—40 MHz OPERATION
AVDD (1.8 V)
TCVDD (1.8 V)
CLIVDD (3 V)
RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)
HVDD1 (3.3 V, 480 pF Total Load on H1 to H8)
DVDD (1.8 V)
DRVDD (3 V, 10 pF Load on Each DOUT Pin)
IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O)
XVVDD (3 V, Depends on Load and Output Frequency of XV Signals)
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Standby1 Mode
Standby2 Mode
Standby3 Mode
MAXIMUM CLOCK RATE (CLI)
Min Typ Max
−25 +85
−65 +150
1.6 1.8
1.6 1.8
1.6 3.0
2.7 3.0
2.7 3.0
1.6 1.8
1.6 3.0
2.7 3.0
2.7 3.0
1.6 1.8
2.25 3.0
2.0
2.0
3.6
3.6
3.6
2.0
3.6
3.6
3.6
2.0
3.6
2.7 3.0 3.6
11.5 15.0 16.5
−8.5 −7.5 −5.5
−1.5 0.0
+1.5
−8.5 −7.5 −5.5
−4.0 0.0
+0.3
27
5
1.5
10
59
9.5
6
2
2
12
5
1.5
40
1 The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation
Total HVDD Power = [CL × HVDD × Pixel Frequency] × HVDD
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CL is the total capacitance seen by all H-outputs.
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
Rev. 0 | Page 3 of 100

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AD9927
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS (IOVDD)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (IOVDD, XVDD, DRVDD)
High Level Output Voltage @ IOH = 2 mA
Low Level Output Voltage @ IOL = 2 mA
RG and H-DRIVER OUTPUTS (HVDD, RGVDD)
High Level Output Voltage @ Maximum Current
Low Level Output Voltage @ Maximum Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (for Each Output)
Symbol Min
VIH VDD − 0.6
VIL
IIH
IIL
CIN
VOH VDD − 0.5
VOL
VOH VDD − 0.5
VOL
18
60
Typ
10
10
10
Max
0.6
0.5
0.5
Unit
V
V
μA
μA
pF
V
V
V
V
mA
pF
Rev. 0 | Page 4 of 100

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AD9927
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 40 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CDS1
Allowable CCD Reset Transient
CDS Gain Accuracy
−3.0 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Maximum Input Range Before Saturation
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Allowable OB Pixel Amplitude1
0 dB CDS Gain (Default)
+6 dB CDS Gain
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Code 15, Default)
Maximum Gain (VGA Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ADC
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Integral Nonlinearity (INL)
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
Peak Nonlinearity, 1.0 V Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Min Typ Max Unit
Notes
0.5 1.2 V
−3.3 −2.8 −2.3 dB
−0.5 0
+0.5 dB
2.4 2.9 3.4 dB
5.0 5.5 6.0 dB
1.4 V p-p
1.0 V p-p
0.7 V p-p
0.5 V p-p
VGA gain = 6.3 dB (Code 15, default value)
VGA gain = 6.3 dB (Code 15, default value)
−100
−50
+200 mV
+100 mV
1024
Guaranteed
Steps
6.3 dB
42.4 dB
1024
0
255
Steps
LSB
LSB
Measured at ADC output
14
−1.0 ±0.5
Guaranteed
4 16
2.0
Bits
LSB
LSB
V
1.4 V
0.4 V
Includes entire signal chain
0 dB CDS gain
5.8 6.3 6.8 dB
Gain = (0.0358 × Code) + 5.76 dB
41.9 42.4 42.9 dB
0.1 0.3 %
6 dB VGA gain, 0 dB CDS gain applied
0.5 LSB rms AC-grounded input, 6 dB VGA gain applied
50 dB Measured with step change on supply
1 Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
200mV MAX
OPTICAL BLACK PIXEL
INPUT
1V MAX
SIGNAL RANGE
(0dB CDS GAIN)
Rev. 0 | Page 5 of 100