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FEATURES
36 MSPS correlated double sampler (CDS)
12-bit 36 MHz A/D converter
On-chip vertical driver for CCD image sensor
On-chip horizontal driver for CCD image sensor
6 dB to 40 dB variable gain amplifier (VGA)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 0.58 ns resolution
2-phase H-clock modes
4-phase vertical transfer clocks
Electronic and mechanical shutter modes
On-chip sync generator with external sync option
64-lead, plastic ball, 9 × 9 grid array Pb-free package
APPLICATION
Digital still cameras
Digital video camcorders
CCD Signal Processor with
Precision Timing™ Generator
AD9929
PRODUCT DESCRIPTION
The AD9929 is a highly integrated CCD signal processor for
digital still camera and digital video camera applications. It
includes a complete analog front end with A/D conversion,
combined with a full-function, programmable timing generator.
The AD9929 also includes horizontal and vertical clock drivers,
which allow direct connection to the CCD image sensor.
The AD9929 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, a CDS, a VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor
gate pulses, a substrate clock, and a substrate bias pulse. Oper-
ation is programmed using a 3-wire serial interface.
The AD9929 is packaged in a 64-lead CSPBGA. It is specified
over an operating temperature range of 25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
AD9929
CDS
6dB TO 40dB
VGA
VREF
ADC
12
DOUT
VSUB
RG
H1, H2
V1, V2,
V3, V4
SUBCK
HORIZONTAL
DRIVERS
2
4
VERTICAL
DRIVERS
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
CLAMP
INTERNAL
REGISTERS
DCLK1
FD/DCLK2
MSHUT
STROBE
HD VD SYNC CLI
Figure 1.
SL SCKS DI
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

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AD9929
TABLE OF CONTENTS
Specifications..................................................................................... 3
Digital Specifications ................................................................... 4
Analog Specifications................................................................... 4
Timing Specifications .................................................................. 5
Vertical Driver Specifications ..................................................... 5
Terminology ...................................................................................... 7
Absolute Maximum Ratings............................................................ 8
Pin Configuration and Functional Descriptions.......................... 9
Equivalent Input Circuits .............................................................. 10
System Overview ............................................................................ 18
Theory of Operation ...................................................................... 19
Modes of Operation ................................................................... 19
Horizontal and Vertical Counters ............................................ 19
CLI Input Clock Divider............................................................ 19
Gray Code Registers................................................................... 19
Serial Interface Timing .............................................................. 20
Analog Front End Description and Operation....................... 22
Precision Timing, High Speed Timing Generation ............... 23
H Driver and RG Outputs ......................................................... 23
Digital Data Outputs.................................................................. 26
External Synchronization (Master Mode)................................... 27
Horizontal and Vertical Synchronous Timing............................ 28
Special Note about the HDLEN Register ................................ 28
Horizontal Clamping and Blanking ............................................. 29
Controlling CLPOB Clamp Pulse Timing .............................. 29
Controlling CLPOB Clamp Pulse Outputs ............................. 30
REVISION HISTORY
Revision A
2/04—Data Sheet Changed from Rev. 0 to Rev. A
Replaced Figure....................................................................................21
1/04—Revision 0: Initial Version
H1 and H2 Blanking .................................................................. 31
VGATE Masking of XV1 to XV4 and CLPOB Outputs............ 33
Vertical Timing Generation .......................................................... 34
Creating Vertical Sequences...................................................... 34
Special Vertical Sweep Mode Operation ................................. 39
Special Vertical Timing (SPATS).............................................. 40
V1 to V4 and SUBCK Output Polarities ..................................... 43
Timing Control............................................................................... 46
Electronic Shutter Timing Control .......................................... 46
VSG Timing ................................................................................ 48
VSUB Timing.............................................................................. 49
MSHUT Timing ......................................................................... 50
Strobe Timing ............................................................................. 52
Digital I/O States for Different Operating Conditions.............. 53
Power Supply Sequencing ............................................................. 54
Recommended Power-Up Supply Sequencing....................... 54
Recommended Power-Down Supply Sequencing ................. 54
Initial Start-Up Sequence .......................................................... 55
Standby Mode Operation .......................................................... 56
Shut-Down Mode Operation.................................................... 57
Applications Where the CLI Clock Frequency Changes
During Operation....................................................................... 58
Circuit Layout Information........................................................... 60
Outline Dimensions ....................................................................... 62
Ordering Guide .......................................................................... 62
Rev. A | Page 2 of 64

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AD9929
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1 to H2 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
VERTICAL DRIVER SUPPLY VOLTAGE
VDD (Vertical Driver Input Logic Supply)
VH1, VH2 (Vertical Driver High Supply)
VM1, VM2 (Vertical Driver Mid Supply)
VL (Vertical Driver Low Supply for 3 Level and 2 Level)
AFETG POWER DISSIPATION
36 MHz, Typ Supply Levels, 100 pF H1 to H2 Loading
Power from HVDD Only1
Power-down Mode (AFE and Digital in Standby Operation)
VERTICAL DRIVER POWER DISSIPATION2 (6000 pF V1 to V4 Loading, 1000 pF SUBCK Loading)
Power from VDD
Power from VH1
Power from VH2
Power from VL
MAXIMUM CLOCK RATE (CLI) AD9929
Min Typ Max
Unit
−25 +85 °C
−65 +150 °C
2.7 3.0 3.6
2.7 3.0 3.6
2.7 3.0 3.6
2.7 3.0 3.6
2.7 3.0 3.6
2.7 3.0 3.6
V
V
V
V
V
V
2.7 3.0 3.6
11.5 15.0 16.0
−1.0 0.0
1.0
−9.0 −7.5 −5.0
V
V
V
V
180 mW
36 mW
1 mW
<1.0
23.0
15.0
42.0
36
mW
mW
mW
mW
MHz
1 The total power dissipated by the HVDD supply may be approximated by using the equation:
Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD × Number of H-Outputs Used.
Actual HVDD power may be slightly different than the calculated value because of the stray capacitance inherent in the PCB layout/routing.
2 Vertical driver loads used when characterizing power consumption. Note: actual power depends on the V1 to V4 timing and number of SUBCKs.
V1, V2, V3, V4
SUBCK
6000 pF
1000 pF
INPUT SIGNAL CHARACTERISTICS DEFINED AS FOLLOWS:
500mV TYP
RESET
TRANSIENT
100mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Rev. A | Page 3 of 64

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AD9929
DIGITAL SPECIFICATIONS
Table 2. RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max Unit
LOGIC INPUTS
High Level Input Voltage
VIH 2.1
V
Low Level Input Voltage
VIL 0.6 V
High Level Input Current
IIH 10 µA
Low Level Input Current
IIL 10 µA
Input Capacitance
CIN 10 pF
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ IOH = 2 mA
VOH 2.2
V
Low Level Output Voltage @ IOL = 2 mA
VOL
0.5 V
RG and H-DRIVER OUTPUTS (H1 to H2)
High Level Output Voltage @ Max Current
VOH VDD − 0.5
V
Low Level Output Voltage @ Max Current
VOL
0.5 V
RG Maximum Output Current (Programmable)
15 mA
H1 and H2 Maximum Output Current (Programmable)
30 mA
Maximum Load Capacitance
100 pF
ANALOG SPECIFICATIONS
Table 3. AVDD = 3.0 V, fCLI = 36 MHz, TMIN to TMAX, unless otherwise noted.
Parameter
Min Typ
Max
CDS
Allowable CCD Reset Transient
500
Max Input Range before Saturation
1.0
Max CCD Black Pixel Amplitude
±100
VARIABLE GAIN AMPLIFIER (VGA)
Max Output Range
2.0
Gain Control Resolution
1024
Gain Monotonicity
Guaranteed
Gain Range
Low Gain
6
Max Gain
40
BLACK LEVEL CLAMP
Clamp Level Resolution
255
Clamp Level
Min Clamp Level
0
Max Clamp Level
255
A/D CONVERTER
Resolution
10
Differential Nonlinearity (DNL)
±0.5
No Missing Codes
Guaranteed
Full-Scale Input Voltage
2.0
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
Reference Bottom Voltage (REFB)
1.0
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code = 22)
6
Max Gain (VGA Code = 994)
40
Peak Nonlinearity, 500 mV Input Signal
0.1
Total Output Noise
0.3
Power Supply Rejection (PSR)
40
Unit
mV
V p–p
mV
V p–p
Steps
dB
dB
Steps
LSB
LSB
LSB
Bits
LSB
V
V
V
dB
dB
%
LSB rms
dB
Notes
See input signal characteristics in Table 1.
LSB measured at ADC output.
Includes entire signal chain.
Gain = (0.035 × Code) + 5.2 dB.
12 dB gain applied.
AC grounded input, 6 dB gain applied.
Measured with step change on supply.
Rev. A | Page 4 of 64

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AD9929
TIMING SPECIFICATIONS
Table 4. CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.
Parameter
Symbol
Min Typ Max Unit
MASTER CLOCK, CLI
CLI Clock Period
tCONV
27.8
ns
CLI High/Low Pulse Width
13.9 ns
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6 ns
AFE CLAMP PULSES1
CLPOB Pulse Width
4 10
Pixels
AFE SAMPLE LOCATION1 (See Figure 17)
SHP Sample Edge to SHD Sample Edge
TS1 20 25
Pixels
DATA OUTPUTS
Output Delay from DCLK1 Rising Edge (See Figure 19)
tOD 9 ns
Pipeline Delay from SHP/SHD Sampling (See Figure 70)
9 Cycles
SERIAL INTERFACE (See Figure 10 and Figure 11)
tDV
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS 10
ns
SCK to SL Hold Time
tLH 10
ns
SDATA Valid to SCK Rising Edge Setup
tDS 10
ns
SCK Falling Edge to SDATA Valid Hold
tDH 10
ns
SCK Falling Edge to SDATA Valid Read
tOD 10
ns
1 Parameter is programmable.
VERTICAL DRIVER SPECIFICATIONS
Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = −7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND,
fCLI = 36 MHz, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max Unit
LOGIC INPUTS
High Level Input Voltage
VIH 0.8 (VDD)
VDD V
Low Level Input Voltage
VIL 0
0.3 (VDD)
V
Propagation Delays, Rise/Fall Times and Output Currents
V1 and V3 Outputs (See Figure 43)
Delay Times
VL to VM1
tPLM1
100 ns
VM1 to VH1
tPMH 100 ns
VH1 to VM1
tPHM 50 ns
VM1 to VL
tPML1
50 ns
Rise Times
VL to VM1
tR1 500 ns
VM1 to VH1
tR2 500 ns
Fall Times
VH1 to VM1
tF1 500 ns
VM1 to VL
tF2 500 ns
Output Currents
V1 or V3 @ VL = −7.25 V
10.0 mA
V1 or V3 @ VM1 = −0.25 V
−5.0 mA
V1 or V3 @ VM1 = +0.25 V
5.0 mA
V1 or V3 @ VH1 = +14.75 V
−7.2 mA
Rev. A | Page 5 of 64