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CS4350
192-kHz Stereo DAC with Integrated PLL
Features
Advanced multibit delta-sigma architecture
109-dB dynamic range
-91-dB THD+N
24-bit conversion
Supports audio sample rates up to 192 kHz
Low-latency digital filtering
Single-ended or differential analog output
architecture
Integrated PLL locks to incoming left-right
clock
– Eliminates the need for external master-
clock routing
– Reduces interference and jitter sensitivity
– No external loop filter components required
Automatic sample-rate range detection
Popguard® technology for control of clicks and
pops
Hardware popguard disable for fast startups
Supports all standard serial audio formats
including time-division multiplexed (TDM)
+1.5- to 5.0-V logic supplies for serial port
+3.3- to 5.0-V control port interface
Control Port Mode Features
SPI™ and I²C Modes
ATAPI mixing
Mute control for individual channels
Digital volume control with soft ramp
– 127.5-dB attenuation
– 0.5-dB step size
– Zero-crossing click-free transitions
3.3 V to 5.0 V
Hardware or I2C/
SPI Control Data
Reset
1.5 V to 5.0 V
Serial Audio Input
LRCK
Recovered MCLK
3.3 V to 5.0 V
Register/
Hardware
Configuration
Interpolation
Filter with
Volume
Control
Multibit 
Modulator
DAC
Amp
+
Filter
Left
Channel
Output
PCM
Serial
Interface
Interpolation
Filter with
Volume
Control
Multibit 
Modulator
DAC
Amp
+
Filter
Right
Channel
Output
RMCK Phase Locked Loop
Internal Voltage
Reference
and Regulation
External
Mute
Control
Left and
Right Mute
Controls
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2006–2015
(All Rights Reserved)
SEPT ‘15
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Description
CS4350
The CS4350 is a complete stereo digital-to-analog system including PLL-based master clock derivation, digital in-
terpolation, 5th-order multibit delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel
mixing, and analog filtering. The advantages of this architecture include ideal differential linearity, no distortion
mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jit-
ter, and a minimal set of external components.
The CS4350 supports all standard digital audio interface formats, including TDM.
The CS4350 is available in a 24-pin QFN package in Commercial grade (-40° to +85°C).
The CS4350 is available in a 24-pin TSSOP package in both Commercial (-40° to +85°C) and Automotive grades
(-40° to +105°C).
The CDB4350 Customer Demonstration board is also available for device evaluation and implementation sugges-
tions. Please refer to “Ordering Information” on page 41 for complete ordering information.
These features are ideal for cost-sensitive, two-channel audio systems, including DVD players and recorders, set-
top boxes, digital TVs, mini-component systems, mixing consoles and automotive audio systems.
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CS4350
TABLE OF CONTENTS
1 PIN DESCRIPTION................................................................................................................................... 6
1.1 TSSOP Pinout ................................................................................................................................. 6
1.2 QFN Pinout ...................................................................................................................................... 6
2 CHARACTERISTICS AND SPECIFICATIONS........................................................................................ 8
2.1 Recommended Operating Conditions ............................................................................................. 8
2.2 Absolute Maximum Ratings ............................................................................................................. 8
2.3 DAC Analog Characteristics - Commercial (-CZZ,-CNZ)................................................................. 9
2.4 DAC Analog Characteristics - Automotive (-DZZ) ......................................................................... 10
2.5 Combined Interpolation and On-Chip Analog Filter Response...................................................... 12
2.6 Switching Specifications - Serial Audio Interface........................................................................... 13
2.7 Switching Characteristics - Control Port - I²C Format.................................................................... 14
2.8 Switching Characteristics - Control Port - SPI Format................................................................... 15
2.9 Digital Characteristics .................................................................................................................... 16
2.10 Power and Thermal Characteristics............................................................................................. 16
3 TYPICAL CONNECTION DIAGRAM ................................................................................................... 17
4 APPLICATIONS ..................................................................................................................................... 18
4.1 Sample Rate Range and Oversampling Mode Detect................................................................... 18
4.1.1 Sample Rate Auto-Detect .................................................................................................... 18
4.2 System Clocking ............................................................................................................................ 18
4.2.1 Recovered Master Clock (RMCK)........................................................................................ 18
4.3 Digital Interface Format ................................................................................................................. 19
4.3.1 Time-Division Multiplex (TDM) Mode ................................................................................... 20
4.4 De-Emphasis ................................................................................................................................. 21
4.5 Mute Control .................................................................................................................................. 21
4.6 Recommended Power-Up Sequence ............................................................................................ 21
4.6.1 Stand-Alone Mode ............................................................................................................... 21
4.6.2 Control Port Mode ................................................................................................................ 22
4.7 Popguard Transient Control .......................................................................................................... 22
4.7.1 Power-Up ............................................................................................................................. 22
4.7.2 Power-Down......................................................................................................................... 22
4.7.3 Discharge Time .................................................................................................................... 22
4.8 Analog Output and Filtering ........................................................................................................... 23
4.9 Grounding and Power Supply Arrangements ................................................................................ 23
4.9.1 Capacitor Placement............................................................................................................ 23
5 STAND-ALONE OPERATION................................................................................................................ 24
5.1 Serial Port Format Selection.......................................................................................................... 24
5.2 De-Emphasis Control .................................................................................................................... 24
5.3 Popguard Transient Control .......................................................................................................... 24
6 CONTROL PORT OPERATION ............................................................................................................. 24
6.1 MAP Auto Increment ..................................................................................................................... 24
6.2 I²C Mode ........................................................................................................................................ 24
6.2.1 I²C Write ............................................................................................................................... 25
6.2.2 I²C Read............................................................................................................................... 25
6.3 SPI Mode ....................................................................................................................................... 26
6.3.1 SPI Write .............................................................................................................................. 26
6.3.2 SPI Read.............................................................................................................................. 26
6.4 Memory Address Pointer (MAP) ................................................................................................... 27
6.4.1 INCR (Auto Map Increment Enable) .................................................................................... 27
6.4.2 MAP (Memory Address Pointer) .......................................................................................... 27
7 REGISTER QUICK REFERENCE .......................................................................................................... 28
8 REGISTER DESCRIPTION .................................................................................................................... 29
8.1 Device and Revision ID - Register 01h.......................................................................................... 29
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8.2 Mode Control - Register 02h ......................................................................................................... 29
8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 29
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 30
8.2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 30
8.3 Volume Mixing and Inversion Control - Register 03h .................................................................... 30
8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 30
8.3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 30
8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 31
8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 31
8.4 Mute Control - Register 04h .......................................................................................................... 32
8.4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 32
8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 32
8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3................................. 32
8.5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 33
8.6 Ramp and Filter Control - Register 07h ......................................................................................... 33
8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 33
8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 ............................................................. 34
8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 ........................................... 34
8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 34
8.7 Misc. Control - Register 08h .......................................................................................................... 34
8.7.1 Power Down (PDN) Bit 7...................................................................................................... 34
8.7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 35
8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 35
8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2 ......................................................................... 35
8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 35
9 FILTER PLOTS ................................................................................................................................... 36
10 PARAMETER DEFINITIONS................................................................................................................ 37
11 PACKAGE DIMENSIONS .................................................................................................................... 38
11.1 24L TSSOP (4.4 mm body) Package Drawing ............................................................................ 38
11.2 24L QFN (4.00 mm BODY) PACKAGE DRAWING..................................................................... 39
12 THERMAL CHARACTERISTICS ......................................................................................................... 39
12.1 QFN Thermal Pad ....................................................................................................................... 40
13 ORDERING INFORMATION ................................................................................................................ 41
14 REVISION HISTORY ........................................................................................................................... 41
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LIST OF FIGURES
Figure 1. Equivalent Output Load .............................................................................................................. 11
Figure 2. Maximum Loading....................................................................................................................... 11
Figure 3. THD+N vs Output Amplitude for VA = 5.0 V ............................................................................... 11
Figure 4. THD+N vs Output Amplitude for VA = 3.3 V ............................................................................... 11
Figure 5. THD+N vs Output Amplitude for VA = 3.14 V ............................................................................. 11
Figure 6. Serial Port Timing, Non-TDM Mode............................................................................................ 14
Figure 7. Serial Port Timing, TDM Mode.................................................................................................... 14
Figure 8. Control Port Timing - I²C Format................................................................................................. 14
Figure 9. Control Port Timing - SPI Mode .................................................................................................. 15
Figure 10. Typical Connection Diagram..................................................................................................... 17
Figure 11. Left-Justified up to 24-Bit Data.................................................................................................. 19
Figure 12. I²S, up to 24-Bit Data ................................................................................................................ 19
Figure 13. Right-Justified Data................................................................................................................... 19
Figure 14. TDM Mode Connection Diagram .............................................................................................. 20
Figure 15. TDM Mode Timing .................................................................................................................... 20
Figure 16. De-Emphasis Curve.................................................................................................................. 21
Figure 17. Differential to Single-Ended Output Filter ................................................................................. 23
Figure 18. Passive Single-Ended Output Filter .......................................................................................... 23
Figure 19. Control Port Timing, I²C Mode .................................................................................................. 26
Figure 20. Control Port Timing, SPI Mode ................................................................................................. 27
Figure 21. De-Emphasis Curve.................................................................................................................. 30
Figure 22. ATAPI Block Diagram ............................................................................................................... 31
Figure 23. Stopband Rejection (fast), all Modes ........................................................................................ 36
Figure 24. Stopband Rejection (slow), all Modes....................................................................................... 36
Figure 25. Single-Speed (fast) Passband Detail ........................................................................................ 36
Figure 26. Single-Speed (slow) Passband Detail....................................................................................... 36
Figure 27. Double-Speed (fast) Passband Detail....................................................................................... 36
Figure 28. Double-Speed (slow) Passband Detail ..................................................................................... 36
Figure 29. Quad-Speed (fast) Passband Detail ......................................................................................... 37
Figure 30. Quad-Speed (slow) Passband Detail........................................................................................ 37
LIST OF TABLES
Table 1. Recommended Operating Conditions ............................................................................................ 8
Table 2. Absolute Maximum Ratings ........................................................................................................... 8
Table 3. DAC Analog Characteristics - Commercial (-CZZ,-CNZ) ............................................................... 9
Table 4. DAC Analog Characteristics - Automotive (-DZZ)........................................................................ 10
Table 5. Combined Interpolation and On-Chip Analog Filter Response .................................................... 12
Table 6. Switching Specifications - Serial Audio Interface ......................................................................... 13
Table 7. Switching Characteristics - Control Port - I²C Format .................................................................. 14
Table 8. Switching Characteristics - Control Port - SPI Format ................................................................. 15
Table 9. Digital Characteristics .................................................................................................................. 16
Table 10. Power and Thermal Characteristics ........................................................................................... 16
Table 11. CS4350 Auto-Detect .................................................................................................................. 18
Table 12. Digital Interface Format - Stand-Alone Mode............................................................................. 24
Table 13. Digital Interface Formats ............................................................................................................ 29
Table 14. ATAPI Decode ........................................................................................................................... 31
Table 15. Example Digital Volume Settings ............................................................................................... 33
Table 16. Thermal Characteristics ............................................................................................................. 39
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