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Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M1025
32 M 1 0 2 6
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
FEATURES
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
19.44 or 38.88
77.76
155.52
622.08
PLL Ratio
(Pin Selectable)
(M1025) (M1026)
8 or 4
2
1
0.25
Output Clock
(MHz)
(Pin Selectable)
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
M1025/26
Loop Filter
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
MUX
0 R Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL
Phase
Detector
M/R Divider
LUT
M Divider
VCSO
P Divider
(1, 2, or TriState)
TriState
LOL
FOUT
nFOUT
2
P_SEL1:0
P Divider
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 1.0
Revised 28Jul2004
M1025/26 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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Integrated
Circuit
Systems, Inc.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O Configuration
Ground
Description
Power supply ground connections.
4
9
5
8
6
7
11, 19, 33
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
Input
Output
Input
Power
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
Power supply connection, connect to +3.3V.
Automatic/manual reselection mode for clock input:
12
AUTO
Input
Internal pull-down resistor1
Logic 1 automatic reselection upon clock failure
(non-revertive)
Logic 0 manual selection only (using REF_SEL)
Reference Acknowledgement pin for input mux state; outputs
13
REF_ACK
Output
the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
15
16
FOUT
nFOUT
Output No internal terminator Clock output pair. Differential LVPECL (CML, LVDS available).
17 P_SEL1
18 P_SEL0
Internal pull-down resistor1
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT), on pg. 4.
20
21
nDIF_REF1
DIF_REF1
Input
Biased to Vcc/2 2
Reference clock input pair 1. Differential LVPECL or LVDS.
Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS.
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
DIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Internal pull-down resistor 1 Resistor bias on inverting terminal supports TTL or LVCMOS.
25 NC
No internal connection.
27
28
29
MR_SEL3
MR_SEL2
MR_SEL0
M and R divider value selection. LVCMOS/ LVTTL.
Input Internal pull-down resistor1 See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
30 MR_SEL1
31 LOL Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
32 NBW Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
34, 35, 36
DNC
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 11.
Table 2: Pin Descriptions
Note 2: Biased toVcc/2, with 50kto Vcc and 50kto ground. See Differential Inputs Biased to VCC/2 on pg. 11.
Note 3: See LVCMOS Output in DC Characteristics on pg. 11.
M1025/26 Datasheet Rev 1.0
2 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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Integrated
Circuit
Systems, Inc.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
DETAILED BLOCK DIAGRAM
M1025/26
OP_IN
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
MUX
0
1
R Div
PLL
Phase
Detector
RIN
R IN
0
1
Auto
Ref Sel
LOL
Phase
Detector
M / R Divider
LUT
RLOOP CLOOP
RLOOP CLOOP
nOP_IN
OP_OUT
Loop Filter
A m plifie r
M Divider
RPOST
R POST
CPOST
CPOST
nOP_OUT nVC
External
Loop Filter
Components
VC
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
P Divider
(1, 2, or TriState)
TriState
2
P_SEL1:0
P Divider
LUT
LOL
FOUT
nFOUT
DIVIDER SELECTION TABLES
Figure 3: Detailed Block Diagram
M and R Divider Look-Up Tables (LUT)
The MR_SEL3:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1025 and M1026 are defined in
Tables 3 and 4 respectively.
M1025 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0000 8 1
8
19.44
19.44
0 0 0 1 32 4
8
19.44
4.86
0 0 1 0 128 16 8
19.44
1.215
0 0 1 1 512 64 8
19.44
0.30375
0100 2 1
2
77.76
77.76
0101 8 4
2
77.76
19.44
0 1 1 0 32 16 2
77.76
4.86
0 1 1 1 128 64 2
77.76
1.215
1000 1 1
1
155.52
155.52
1001 4 4
1
155.52
38.88
1 0 1 0 16 16 1
155.52
9.72
1 0 1 1 64 64 1
1 1 0 0 Test Mode1 N/A
155.52
N/A
2.43
N/A
1101 1
4 0.25
622.08
155.52
1 1 1 0 4 16 0.25
622.08
38.88
1 1 1 1 16 64 0.25
622.08
9.72
Table 3: M1025 M/R Divider LUT
Note 1: Factory test mode; do not use.
ables 3 and 4 provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (M1025-11-155.5200 and M1026-11-155.5200).
See “Ordering Information” on pg. 14.
M1026 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0000 4 1
4
38.88
38.88
0 0 0 1 16 4
4
38.88
9.72
0 0 1 0 64 16
4
38.88
2.43
0 0 1 1 256 64
4
38.88
0.6075
0100 2 1
2
77.76
77.76
0101 8 4
2
77.76
19.44
0 1 1 0 32 16
2
77.76
4.86
0 1 1 1 128 64
2
77.76
1.215
1000 1 1
1
155.52
155.52
1001 4 4
1
155.52
38.88
1 0 1 0 16 16
1
155.52
9.72
1 0 1 1 64 64
1
1 1 0 0 Test Mode1 N/A
155.52
N/A
2.43
N/A
1 1 0 1 1 4 0.25 622.08
155.52
1 1 1 0 4 16 0.25 622.08
38.88
1 1 1 1 16 64 0.25 622.08
9.72
Table 4: M1026 M/R Divider LUT
Note 1: Factory test mode; do not use.
M1025/26 Datasheet Rev 1.0
3 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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Integrated
Circuit
Systems, Inc.
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the LOL
output for clock fault detection.
P Divider Look-Up Table (LUT)
The P_SEL1 and P_SEL0 pins select the post-PLL divider
value P. The output frequency of the SAW can be
divided by 1 or 2 or the output can be TriStated as
specified in Table 5.
P_SEL1:0
00
01
10
11
P Value
M1025-155.5200 or M1026-155.5200
Output Frequency (MHz)
2 77.76
1 155.52
2 77.76
TriState
N/A
Table 5: P Divider Look-Up Table (LUT)
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
FUNCTIONAL DESCRIPTION
The M1025/26 is a PLL (Phase Locked Loop) based
clock generator that generates an output clock synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Tables 3 and 4 on pg. 3. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1025/26 includes a Loss of Lock (LOL) indicator,
which provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1025/26. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails. Reference selection is
non-revertive, meaning that only one reference
reselection will be made each time that AutoSwitch is
re-enabled.
In addition to the AutoSwitch feature, Hitless Switching
and Phase Build-out options can be ordered with the
device. The Hitless Switching and Phase Build-out
options help assure SONET/SDH MTIE and TDEV
compliance during either a manual or automatic input
reference reselection.
M1025/26 Datasheet Rev 1.0
4 of 14
Revised 28Jul2004
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Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Implementation of single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50kto Vcc and 50kto ground. Figure 4 shows
the input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
LVCMOS/
LVTTL
DIF_REF0
nDIF_REF0
X
VCC
DIF_REF1 127
LVPECL
VCC
82
127
nDIF_REF1
82
REF_SEL
VCC
50k
50k
50k
VCC
50k
50k
50k
MUX
0
1
M1025/26
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127
and 82resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
PLL Operation
The M1025/26 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
Fvcso
=
Fin
×
M---
R
For the available M divider and R divider look-up table
combinations, Tables 3 and 4 on pg. 3 list the Total PLL
Ratio as well as Fin when using the M1025-11-155.5200 or
the M1026-11-155.5200. (“Ordering Information”, pg. 14.)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1025/26 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The P_SEL pin selects the value for the P divider: logic 1
sets P to 2, logic 0 sets P to 1. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Fout = --F----v---c---s---o---- = Fin × ------M-----------
P R× P
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M1025/26 Datasheet Rev 1.0
5 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400