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LTC2284
Dual 14-Bit, 105Msps
Low Power 3V ADC
FEATURES
Integrated Dual 14-Bit ADCs
Sample Rate: 105Msps
Single 3V Supply (2.85V to 3.4V)
Low Power: 540mW
72.4dB SNR, 88dB SFDR
110dB Channel Isolation at 100MHz
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
64-Pin (9mm × 9mm) QFN Package
U
APPLICATIO S
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
DESCRIPTIO
The LTC®2284 is a 14-bit 105Msps, low power dual 3V
A/D converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2284 is perfect for
demanding imaging and communications applications
with AC performance that includes 72.4dB SNR and 85dB
SFDR for signals at the Nyquist frequency.
Typical DC specs include ±1.5LSB INL, ±0.6LSB DNL. The
transition noise is a low 1.3LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
ANALOG
INPUT A
+
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
CLK A
CLK B
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
ANALOG
INPUT B
+
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
OVDD
D13A
•••
D0A
OGND
MUX
OUTPUT
DRIVERS
OVDD
D13B
•••
D0B
OGND
2284 TA01
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
72
71
70
69
68
67
66
65
0
50 100 150 200 250 300 350
INPUT FREQUENCY (MHz) 2284 TA01b
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LTC2284
ABSOLUTE AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2284C ............................................... 0°C to 70°C
LTC2284I .............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
UW U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
48 DA7
47 DA6
46 DA5
REFHA 4
45 DA4
REFLA 5
44 DA3
REFLA 6
43 DA2
VDD 7
42 DA1
CLKA 8
CLKB 9
65
41 DA0
40 OFB
VDD 10
REFLB 11
39 DB13
38 DB12
REFLB 12
37 DB11
REFHB 13
36 DB10
REFHB 14
AINB– 15
AINB+ 16
35 DB9
34 DB8
33 DB7
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
LTC2284CUP
LTC2284IUP
QFN PART*
MARKING
LTC2284UP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Resolution
14 Bits
Integral Linearity Error
Differential Linearity Error
Differential Analog Input (Note 5)
Differential Analog Input
±1.5 LSB
±0.6 LSB
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
(Note 6)
External Reference
Internal Reference
External Reference
External Reference
SENSE = 1V
–12 ±2
–2.5 ±0.5
±10
±30
±5
±0.3
±2
1.3
12 mV
2.5 %FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSBRMS
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LTC2284
A ALOG I PUT The denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
VIN
VIN,CM
IIN
ISENSE
IMODE
tAP
tJITTER
CMRR
PARAMETER
Analog Input Range (AIN+ –AIN–)
Analog Input Common Mode (AIN+ +AIN–)/2
Analog Input Leakage Current
SENSEA, SENSEB Input Leakage
MODE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
CONDITIONS
2.85V < VDD < 3.4V (Note 7)
Differential Input Drive (Note 7)
Single Ended Input Drive (Note 7)
0V < AIN+, AIN– < VDD
0V < SENSEA, SENSEB < 1V
0V < MODE < VDD
Figure 8 Test Circuit
MIN TYP
MAX
±0.5V to ±1V
1
0.5
1.5
1.5
1.9
2
–1
1
–3
3
–3
3
0
0.2
80
575
UNITS
V
V
V
µA
µA
µA
ns
psRMS
dB
MHz
DY A IC ACCURACY The denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio
5MHz Input
72.4 dB
30MHz Input
72.3 dB
70MHz Input
69.4 72.2
dB
140MHz Input
71.7 dB
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
30MHz Input
88 dB
86 dB
70MHz Input
72 84
dB
140MHz Input
80 dB
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
30MHz Input
90 dB
90 dB
70MHz Input
80 90
dB
140MHz Input
90 dB
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
5MHz Input
72.2 dB
30MHz Input
72.1 dB
70MHz Input
68.4 71.9
dB
140MHz Input
70.5 dB
IMD Intermodulation Distortion
fIN = 40MHz,
41MHz
85 dB
Crosstalk
fIN = 100MHz
–110 dB
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LTC2284
UU
U
I TER AL REFERE CE CHARACTERISTICS (Note 4)
PARAMETER
VCM Output Voltage
VCM Output Tempco
VCM Line Regulation
VCM Output Resistance
CONDITIONS
IOUT = 0
2.85V < VDD < 3.4V
–1mA < IOUT < 1mA
MIN
1.475
TYP
1.500
±25
3
4
MAX
1.525
UNITS
V
ppm/°C
mV/V
DIGITAL I PUTS A D DIGITAL OUTPUTS The denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
VIH
VIL
IIN
CIN
LOGIC OUTPUTS
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
VDD = 3V
VDD = 3V
VIN = 0V to VDD
(Note 7)
2
0.8
–10
10
3
V
V
µA
pF
OVDD = 3V
COZ
ISOURCE
ISINK
VOH
VOL
OVDD = 2.5V
VOH
VOL
OVDD = 1.8V
VOH
VOL
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
OE = High (Note 7)
VOUT = 0V
VOUT = 3V
IO = –10µA
IO = –200µA
IO = 10µA
IO = 1.6mA
IO = –200µA
IO = 1.6mA
IO = –200µA
IO = 1.6mA
3
50
50
2.995
2.7 2.99
0.005
0.09 0.4
2.49
0.09
1.79
0.09
pF
mA
mA
V
V
V
V
V
V
V
V
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LTC2284
POWER REQUIRE E TS The denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD Analog Supply Voltage
(Note 9)
2.85 3 3.4
V
OVDD
Output Supply Voltage
(Note 9)
0.5 3 3.6
V
IVDD
PDISS
Supply Current
Power Dissipation
Both ADCs at fS(MAX)
Both ADCs at fS(MAX)
180 210
mA
540 630
mW
PSHDN
Shutdown Power (Each Channel)
SHDN = H, OE = H, No CLK
2 mW
PNAP Nap Mode Power (Each Channel)
SHDN = H, OE = L, No CLK
15 mW
WU
TI I G CHARACTERISTICS The denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
tL
PARAMETER
Sampling Frequency
CLK Low Time
tH CLK High Time
tAP
tD
tMD
Pipeline Latency
Sample-and-Hold Aperture Delay
CLK to DATA Delay
MUX to DATA Delay
Data Access Time After OE
BUS Relinquish Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
(Note 7)
MIN TYP MAX
1
105
4.5 4.76 500
3 4.76 500
4.5 4.76 500
3 4.76 500
0
1.4 2.7 5.4
1.4 2.7 5.4
4.3 10
3.3 8.5
6
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 105MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 105MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
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