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CS1088
Vacuum Fluorescent
Display Tube Driver
The VFD Driver is a microprocessor interface IC that drives a
multiplexed VF (Vacuum Fluorescent) display tube. It consists of a
34–bit shift register, a 34–bit transparent data latch, a metal mask
ROM, six 20 mA anode output drivers, twenty–five 2 mA anode
output drivers, and three 50 mA grid drivers with output enables.
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Features
Power On Reset
Display Dimming Possible
Three, 50 mA Grid Drivers
Anodes:
6 @ 20 mA
25 @ 2 mA
VIGN 12 V
Regulator
5V
GND
VBAT
VCC
µP
PORT
PORT
PORT
GND PORT
Chip Select
Clock
SPI Functions
0.1 µF VBB
CS1088
Anodes
1:31
FILAMENT
VFD
GRID1GRID2 GRID3 GND
DIN GRID1
CLK GRID2
STB GRID3
GREN
GND
40
1
DIP–40
WIDE BODY
N SUFFIX
CASE 711
ORDERING INFORMATION*
Device
CS1088XN40
Package
DIP–40
WIDE BODY
Shipping
9 Units/Rail
*For additional package options, consult your local
ON Semiconductor sales office.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Figure 1. Application Diagram
© Semiconductor Components Industries, LLC, 2001
August, 2001 – Rev. 9
1
Publication Order Number:
CS1088/D

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CS1088
MAXIMUM RATINGS*
Supply Voltage (VBB)
Input Voltages (DIN, CLK, STB, GREN)
Junction Temperature Range
Storage Temperature Range
ESD Susceptibility (Human Body Model)
ESD Susceptibility (Machine Model)
Package Thermal Resistance, DIP–40
Junction–to–Case, RθJC
Junction–to–Ambient, RθJA
Lead Temperature Soldering:
Parameter
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Value
–0.6 to +18
–0.6 to +6.0
–40 to +150
–55 to +150
2.0
200
Wave Solder (through hole styles only) Note 1
Reflow (SMD styles only) Note 2
20
45
260 Peak
230 Peak
Unit
V
V
°C
°C
kV
V
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (8.0 V VBB 16.5 V, Gnd = 0 V, –40°C TJ 105°C; unless otherwise stated. Note 3.)
Parameter
Test Conditions
Min Typ Max Unit
VBB Input
VBB Input Voltage
IBB0 Current
Reset Mode
No outputs active, VBB = 16.5 V
All outputs forced low.
8.0 – 16.5 V
– 2.0 5.0 mA
– 6.5 7.5 V
DIN, CLK, STB Inputs
VIL1, Input Low Voltage
VIH, Input High Voltage
IIL, Input Current
GREN Input
VIN = VIH
– – 1.6 V
3.3 – – V
– 7.5 20.0 µA
VIL, Input Low Voltage
VIH, Input High Voltage
IIH, Input Pull–down Current
GRID1, GRID2, GRID3 Outputs
VIN = 3.325 V
– – 1.6 V
3.3 – – V
– 30 60 µA
IOL
IOH
VOL
VOH
AN24 – AN29 Outputs
Sink Current
Source Current
IOUT = 1.0 mA
IOUT = –50 mA, VBB = 12 V
1.0
50
VBB – 0.75
– mA
– mA
0.5 V
VBB V
IOL
Sink Current
400 –
µA
IOH
Source Current
20 –
– mA
VOL
IOUT = 400 µA
– – 0.5 V
VOH
IOUT = –20 mA, VBB = 12 V
VBB – 0.5
VBB
V
3. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
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CS1088
ELECTRICAL CHARACTERISTICS (continued) (8.0 V VBB 16.5 V, Gnd = 0 V, –40°C TJ 105°C; unless otherwise stated.
Note 4.)
Parameter
Test Conditions
Min Typ Max Unit
AN1 – AN23 Outputs
IOL Sink Current
IOH Source Current
VOL IOUT = 100 µA
VOH
IOUT = –2.0 mA, VBB = 12 V
AC Characteristics: Input and Output Timing
100
2.0
VBB – 0.5
µA
– mA
0.5 V
VBB V
FC, CLK Frequency
TCL, CLK Low Time
TCH, CLK High Time
TCR, CLK Rise Time
TCF, CLK Fall Time
TSC, STB Low to CLK High Time
TST, STB High Time
TAN, STB High to Anode Output
Propagation Delay
– 0 – 1.0 MHz
200 –
– ns
200 –
– ns
– – – 100 ns
– – – 100 ns
50 –
– ns
500 –
– ns
– – – 5.0 µs
TGL, Grid Turn On Propagation Delay VBB = 12 V
– – 2.0 µs
TG0, Grid Turn Off Propagation Delay VBB = 12 V
– – 5.0 µs
TGR, Grid Rise Time
At rated load. Note 5
0.50 – 2.00 µs
TGF, Grid Fall Time
At rated load. Note 5
0.35 – 2.00 µs
TAR, Anode Rise Time
At rated load. Note 5
0.40 – 2.00 µs
TAF, Anode Fall Time
At rated load. Note 5
0.40 – 2.50 µs
4. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
5. Grid and anode rise / fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the
respective stages.
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CS1088
PACKAGE LEAD DESCRIPTION
Package Lead Number
Lead Symbol
40L DIP
(31 Anode Configuration)
1 GRID1
2 GRID2
3 GRID3
4 AN1
5 AN2
6 AN3
7 AN4
8 AN5
9 AN6
10 AN7
11 AN8
12 AN9
13 AN10
14 AN11
15 AN12
16 AN13
17 AN14
18 AN15
19 AN16
20 GND
21 AN17
22 AN18
23 AN19
24 AN20
25 AN21
26 AN22
27 AN23
28 AN24
29 AN25
30 AN26
31 AN27
32 AN28
33 AN29
34 AN30
35 DIN
36 CLK
37 STB
38 GREN
39 AN31
40 VBB
50 mA grid output.
Function
50 mA grid output.
50 mA grid output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
Ground connection.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
2.0 mA anode output.
Shift register data input.
Shift register clock input.
Transfer contents of shift registers to output stages.
Grid outputs enable.
2.0 mA anode output.
Supply voltage input.
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CS1088
GRID1 GRID2 GRID3 AN1 AN2 AN3
AN25 AN26 AN27 AN28 AN29 AN30 AN31
VBB
GND
POR
VREG
VREG
GREN
VREG
STB
VREG
DIN
VREG
CLK
VREG
METAL MASK ROM
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ DQ
LE LE
DQ
LE
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
Output Drive Capability
Grid Outputs: 50 mA
AN24 – AN29: 20 mA
AN1 – AN23, AN30, AN31: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the DIN pin at the rising
edge of the CLK input. Thirty four bits of data are capable
of being stored by the shift register. Once the desired pattern
is stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN31 are always enabled.
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