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CS1089
Vacuum Fluorescent
Display Tube Driver
The VFD Driver is a microprocessor interface IC that drives a
multiplexed VF (Vacuum Fluorescent) display tube. It consists of a
32–bit shift register, a 32–bit transparent data latch, a metal mask
ROM, six 20 mA anode output drivers, twenty–three 2 mA anode
output drivers, and three 50 mA grid drivers with output enables.
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Features
Power On Reset
Display Dimming Possible
Three, 50 mA Grid Drivers
Anodes:
6 @ 20 mA
23 @ 2 mA
VIGN 12 V
Regulator
5V
GND
VBAT
VCC
µP
PORT
PORT
PORT
GND PORT
Chip Select
Clock
Data Out
SPI Functions
Anodes
1:29
0.1 µF VBB
CS1089
FILAMENT
VFD
GRID1GRID2 GRID3 GND
DOUT
DIN GRID1
CLK GRID2
STB GRID3
GREN
GND
40
1
DIP–40
WIDE BODY
N SUFFIX
CASE 711
PLCC–44
FN SUFFIX
CASE 777
ORDERING INFORMATION
Device
CS1089XN40
Package
DIP–40
WIDE BODY
CS1089XFN44
CS1089XFNR44
PLCC–44
PLCC–44
Shipping
9 Units/Rail
23 Units/Rail
500 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Figure 1. Application Diagram
© Semiconductor Components Industries, LLC, 2001
August, 2001 – Rev. 9
1
Publication Order Number:
CS1089/D

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CS1089
MAXIMUM RATINGS*
Supply Voltage (VBB)
Input Voltages (DIN, CLK, STB, GREN)
Junction Temperature Range
Storage Temperature Range
ESD Susceptibility (Human Body Model)
ESD Susceptibility (Machine Model)
Package Thermal Resistance, DIP–40
Junction–to–Case, RθJC
Junction–to–Ambient, RθJA
Package Thermal Resistance, PLCC–44
Junction–to–Case, RθJC
Junction–to–Ambient, RθJA
Lead Temperature Soldering:
Parameter
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Value
–0.6 to +18
–0.6 to +6.0
–40 to +150
–55 to +150
2.0
200
20
45
Wave Solder (through hole styles only) Note 1
Reflow (SMD styles only) Note 2
16
55
260 Peak
230 Peak
Unit
V
V
°C
°C
kV
V
°C/W
°C/W
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (8.0 V VBB 16.5 V, Gnd = 0 V, –40°C TJ 105°C; unless otherwise stated. Note 3.)
Parameter
Test Conditions
Min Typ Max Unit
VBB Input
VBB Input Voltage
IBB0 Current
Reset Mode
No outputs active, VBB = 16.5 V
All outputs forced low.
8.0 – 16.5 V
– 2.0 5.0 mA
– 6.5 7.5 V
DIN, CLK, STB Inputs
VIL1, Input Low Voltage
VIH, Input High Voltage
IIL, Input Current
GREN Input
VIN = VIH
– – 1.6 V
3.3 – – V
– 7.5 20.0 µA
VIL, Input Low Voltage
VIH, Input High Voltage
IIH, Input Pull–down Current
GRID1, GRID2, GRID3 Outputs
VIN = 3.325 V
– – 1.6 V
3.3 – – V
– 30 60 µA
IOL
IOH
VOL
VOH
AN24 – AN29 Outputs
Sink Current
Source Current
IOUT = 1.0 mA
IOUT = –50 mA, VBB = 12 V
1.0
50
VBB – 0.75
– mA
– mA
0.5 V
VBB V
IOL
Sink Current
400 –
µA
IOH
Source Current
20 –
– mA
VOL
IOUT = 400 µA
– – 0.5 V
VOH
IOUT = –20 mA
VBB – 0.5
VBB
V
3. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
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CS1089
ELECTRICAL CHARACTERISTICS (continued) (8.0 V VBB 16.5 V, Gnd = 0 V, –40°C TJ 105°C; unless otherwise stated.
Note 4.)
Parameter
Test Conditions
Min Typ Max Unit
AN1 – AN23 Outputs
IOL Sink Current
IOH Source Current
VOL IOUT = 100 µA
VOG
IOUT = –2.0 mA
DOUT Output
IOL Sink Current
IOH Source Current
VOL IOUT = 1.0 mA
VOH
IOUT = –1.0 mA
AC Characteristics: Input and Output Timing
100
2.0
VBB – 0.5
1.0
1.0
3.9
µA
– mA
0.5 V
VBB V
– mA
– mA
0.5 V
5.1 V
FC, CLK Frequency
TCL, CLK Low Time
TCH, CLK High Time
TCR, CLK Rise Time
TCF, CLK Fall Time
TCD, CLK Low to DOUT
Propagation Delay
– 0 – 1.0 MHz
200 –
– ns
200 –
– ns
– – – 100 ns
– – – 100 ns
– – – 200 ns
TSC, STB Low to CLK High Time
TST, STB High Time
TAN, STB High to Anode Output
Propagation Delay
50 –
– ns
500 –
– ns
– – – 5.0 µs
TGL, Grid Turn On Propagation Delay VBB = 12 V
– – 2.0 µs
TG0, Grid Turn Off Propagation Delay VBB = 12 V
– – 5.0 µs
TGR, Grid Rise Time
At rated load. Note 5.
0.50 – 2.00 µs
TGF, Grid Fall Time
At rated load. Note 5.
0.35 – 2.00 µs
TAR, Anode Rise Time
At rated load. Note 5.
0.40 – 2.00 µs
TAF, Anode Fall Time
At rated load. Note 5.
0.40 – 2.50 µs
4. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
5. Grid and anode rise / fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the
respective stages.
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PACKAGE LEAD DESCRIPTION
Package Lead Number
40L DIP
44L PLCC
1 14
2 15
3 16
4 17
5 18
6 19
7 20
8 21
9 22
10 24
11 25
12 26
13 27
14 28
15 29
16 30
17 31
18 32
19 33
20 35
21 36
22 37
23 38
24 39
25 40
26 41
27 42
28 43
29 44
30 2
31 3
32 4
33 5
34 6
35 7
36 8
37 9
38 10
39 1, 11, 12, 23, 34
40 13
CS1089
Lead Symbol
(29 Anode Configuration)
Function
GRID1
50 mA grid output.
GRID2
50 mA grid output.
GRID3
50 mA grid output.
AN1 2.0 mA anode output.
AN2 2.0 mA anode output.
AN3 2.0 mA anode output.
AN4 2.0 mA anode output.
AN5 2.0 mA anode output.
AN6 2.0 mA anode output.
AN7 2.0 mA anode output.
AN8 2.0 mA anode output.
AN9 2.0 mA anode output.
AN10
2.0 mA anode output.
AN11
2.0 mA anode output.
AN12
2.0 mA anode output.
AN13
2.0 mA anode output.
AN14
2.0 mA anode output.
AN15
2.0 mA anode output.
AN16
2.0 mA anode output.
GND
Ground connection.
AN17
2.0 mA anode output.
AN18
2.0 mA anode output.
AN19
2.0 mA anode output.
AN20
2.0 mA anode output.
AN21
2.0 mA anode output.
AN22
2.0 mA anode output.
AN23
2.0 mA anode output.
AN24
20 mA anode output.
AN25
20 mA anode output.
AN26
20 mA anode output.
AN27
20 mA anode output.
AN28
20 mA anode output.
AN29
20 mA anode output.
DOUT
DIN
CLK
Shift register data output.
Shift register data input.
Shift register clock input.
STB Transfer contents of shift registers to output stages.
GREN
Grid outputs enable.
NC No connection.
VBB Supply voltage input.
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CS1089
GRID1 GRID2 GRID3 AN1 AN2 AN3
VBB
GND
POR
VREG
VREG
AN23 AN24 AN25 AN26 AN27 AN28 AN29
GREN
VREG
STB
VREG
DIN
VREG
CLK
VREG
METAL MASK ROM
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
LE
VREG
DQ
CLK
R
DOUT
Output Drive Capability
Grid Outputs: 5 mA
AN24 – AN29: 20 mA
AN1 – AN23: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the DIN pin at the rising
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
The DOUT pin is the output of the last stage of the shift
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on
the DOUT output changes with the falling edges of the CLK
to prevent logic race conditions between the CLK and the
DIN of the next IC in the serial chain.
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