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September 1998
54AC574 54ACT574
Octal D-Type Flip-Flop with TRI-STATE® Outputs
General Description
The ’AC/’ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered common
Output Enable (OE). The information presented to the D in-
puts is stored in the flip-flops on the LOW-to-HIGH Clock
(CP) transition.
The ’AC/’ACT574 is functionally identical to the ’AC/’ACT374
except for the pinouts.
Features
n ICC and IOZ reduced by 50%
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’AC/’ACT374
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT574 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’ACT574: 5962-89601
Logic Symbols
IEEE/IEC
DS100256-1
DS100256-4
Pin Names
D0– D7
CP
OE
O0– O7
Description
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100256
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Connection Diagrams
Pin Assignment for DIP,
and Flatpak
DS100256-2
Pin Assignment
for LCC
DS100256-3
Functional Description
The ’AC/’ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and buffered Output Enable are common
to all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
go to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs Internal Outputs
OE CP D
H HL
Q
NC
ON
Z
H H H NC
Z
H NL
L
Z
H NH
H
Z
L NL
L
L
L NH
H
H
L H L NC
NC
L H H NC
NC
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
Function
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
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Logic Diagram
DS100256-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
Recommended Operating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC +0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC +0.5V
DC Output Voltage (VO)
DC Output Source or Sink Current
(IO)
DC VCC or Ground Current
Per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC +0.5V
−20 mA
+20 mA
−0.5V to VCC +0.5V
±50 mA
±50 mA
−65˚C to +150˚C
175˚C
Conditions
Supply Voltage (VCC)
(Unless Otherwise Specified) (AC)
2.0V to 6.0V
(ACT)
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54AC/ACT
0V to VCC
0V to VCC
−55˚C to +125˚C
Minimum Input Edge Rate (V/t)
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (V/t)
125 mV/ns
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTcircuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
Symbol
Parameter
VCC
TA =
(V) −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
VIH Minimum High
Level Input
Voltage
3.0
4.5
5.5
2.1
3.15
3.85
VOUT = 0.1V
V or VCC − 0.1V
VIL Maximum Low
Level Input
Voltage
3.0
4.5
5.5
0.9
1.35
1.65
VOUT = 0.1V
V or VCC − 0.1V
VOH Minimum High
Level Output
3.0
4.5
2.9
4.4
IOUT = −50 µA
V
Voltage
5.5 5.4
3.0 2.4
(Note 2)
VIN = VIL or VIH
−12 mA
4.5 3.7
5.5 4.7
V IOH −24 mA
−24 mA
VOL Maximum Low
Level Output
3.0
4.5
0.1
0.1
IOUT = 50 µA
V
Voltage
5.5 0.1
3.0 0.50
(Note 2)
VIN = VIL or VIH
12 mA
4.5 0.50
5.5 0.50
V IOL 24 mA
24 mA
IIN Maximum Input
5.5
Leakage Current
±1.0
µA VI = VCC, GND
IOZ Maximum
TRI-STATE
Leakage Current
5.5
±5.0
VI (OE) = VIL, VIH
µA VI = VCC, VGND
VO = VCC, GND
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DC Characteristics for ’AC Family Devices (Continued)
Symbol
IOLD
IOHD
ICC
Parameter
(Note 3) Minimum
Dynamic Output
Current
Maximum Quiescent
Supply Current
VCC
(V)
5.5
5.5
5.5
54AC
TA =
−55˚C to +125˚C
Guaranteed Limits
50
−50
80.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VIH Minimum High
Level Input
Voltage
VIL Maximum Low
Level Input
Voltage
VOH Minimum High
Level
54ACT
VCC
TA =
(V) −55˚C to +125˚C
Guaranteed Limits
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 4.4
5.5 5.4
Units
mA
mA
µA
Units
V
V
V
VOL Maximum Low
Level Output
Voltage
4.5
5.5
4.5
5.5
3.70
4.70
0.1
0.1
IIN
IOZ
ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
Maximum
TRI-STATE
Leakage Current
Maximum ICC/Input
(Note 5) Minimum
Dynamic Output
Current
Maximum Quiescent
Supply Current
4.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Note 4: All outputs loaded; thresholds on input associated with output under test.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
0.50
0.50
±1.0
±5.0
1.6
50
−50
80.0
V
V
V
µA
µA
mA
mA
mA
µA
Conditions
VOLD = 1.65V
VOHD = 3.85V
VIN = VCC
or GND
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
(Note 4)
VIN = VIL or VIH
IOH −24 mA
−24 mA
IOUT = 50 µA
(Note 4)
VIN = VIL or VIH
IOL 24 mA
24 mA
VI = VCC, GND
VI = VIL, VIH
VO = VCC, GND
VI = VCC − 2.1V
VOLD = 1.65V
VOHD = 3.85V
VIN = VCC
or GND
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