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DS1610
Partitioned NV Controller
FEATURES
PIN ASSIGNMENT
Converts CMOS RAMs into nonvolatile
memories
SOIC version is pin-compatible with the
Dallas Semiconductor DS1210 NV Controller
Unconditionally write protects all of memory
when VCC is out of tolerance
Write protects selected blocks of memory
regardless of VCC status when programmed
Automatically switches to battery backup
supply when power-fail occurs
AW
VCCO
AX
VBAT1
AY
TOL
DIS
GND
1
2
3
4
5
6
7
8
16 PFO
15 VCCI
14 AZ
13 VBAT2
12 WEO
11 CEO
10 WEI
9 CEI
16-Pin DIP and 16-Pin SOIC
Provides for multiple batteries
Consumes less than 100 nA of battery current
Test battery on power-up by inhibiting the
second memory cycle
Optional 5% or 10% power-fail detection
16-pin DIP or 16-pin SOIC surface-mount
package
Low forward voltage drop on the VCC switch
with currents of up to 150 mA
Optional industrial temperature range of
-40°C to +85°C
PIN DESCRIPTION
VCCI
VBAT1
VBAT2
VCCO
GND
- Input +5 Volt Supply
- + Battery 1 Input
- + Battery 2 Input
- RAM Power (VCC) Supply
- Ground
CEI - Chip Enable Input
CEO - Chip Enable Output
WEI - Write Enable Input
WEO
- Write Enable Output
TOL
- Power Supply Tolerance Select
AW - AZ
- Address Inputs
DIS - Memory Partition Disable
PFO - Power-Fail Output
DESCRIPTION
The DS1610 is a low-power CMOS circuit which solves the application problems of converting CMOS
RAMS into nonvolatile memories. In addition the device has the ability to unconditionally write protect
blocks of memory so that inadvertent write cycles do not corrupt program and special data space. The
power supply incoming voltage at the VCCI input pin is constantly monitored for an out-of-tolerance
condition. When such a condition is detected, both the chip enable and write enable outputs are inhibited
to protect stored data. The battery inputs are used to supply VCCO with power when VCCI is less than the
battery input voltages. Special circuitry uses a low leakage CMOS process which affords precise voltage
detection at extremely low current consumption. By combining the DS1610 Partitioned NV Controller
chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved.
The DS1610 Partitioned NV Controller functions like the Dallas Semiconductor DS1210 NV controller
when the ( DIS) disable pin is grounded. An internal pulldown resistor to ground on the DIS pin of the
DS1610S allows it to retrofit into DS1210S applications. When the DIS pin is grounded the address
inputs AW - AZ and the write enable input WEI are ignored. Also the power-fail output PFO and the write
enable output WEO are tristated.
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DS1610
OPERATION - DISABLE PIN CONNECTED TO VCCO
The DS1610 performs five circuit functions required to battery backup a RAM. First, a switch is provided
to direct power from the battery or the incoming power supply (VCCI) depending on which is greater. This
switch has a voltage drop of less than 0.2 volts. The second function provided by the DS1610 is power-
fail detection. The incoming supply (VCCI) is constantly monitored. When the supply goes out of
tolerance a precision comparator detects power failure and inhibits both the chip enable output ( CEO ) and
the write enable output ( WEO ). A third function of write protection is accomplished by holding both the
chip enable output CEO and write enable output WEO to within 0.2 volts of VCCO when VCCI is out of
tolerance. If CEI is low at the time that power-fail detection occurs the CEO signal is kept low until CEI
is brought high again. However, CEO is forced high after 1.5 µs regardless of the state of CEI . Similarly,
if WEI is low at the time that power fail detection occurs, the WEO signal will remain low until WEI is
brought high or 1.5 µs elapses. The delay of write protection until the current memory cycle is complete
prevents corrupted data. Power-fail detection occurs in the range of 4.75 to 4.5 volts with the tolerance
pin TOL grounded. If the tolerance pin is connected to VCCO then power-fail detection occurs in the range
of 4.5 volts to 4.25 volts. The PF0 signal is driven low and remains low until VCCI returns to nominal
conditions. During nominal supply conditions CEO will follow CEI and WEO will follow WEI . The
fourth function which the DS1610 performs is a battery status warning so that potential data loss is
avoided. Each time VCCI is applied to the device battery status is checked with a precision comparator. If
during battery backup no switch occurred from one battery to the other, the voltage of the battery
supplying power when VCCI is applied is checked. If this voltage is less than 2.0 volts the second chip
enable cycle after power is applied is inhibited. If any switch from one battery to another did occur the
voltage of both batteries is checked. If either voltage is less than 2.0 volts the second chip enable cycle
will be inhibited. Battery status can therefore be determined by performing a read cycle after power up to
any location in memory, verifying that memory location’s contents. A subsequent write cycle can then be
executed to the same memory location altering the data. If the next read cycle fails to verify the written
data then the data is in danger of being corrupted. The fifth function of the DS1610 provides for battery
redundancy. When data integrity is extremely important it is wise to use two batteries to insure reliability.
The DS1610 controller provides an internal isolation switch which allows the connection of two batteries.
When entering battery backup operation, the battery with the highest voltage is selected for use. If one
battery should fail, the other would then supply energy to the connected load. The switch to a redundant
battery is transparent to circuit operation and to the user. In applications where battery redundancy is not
a major concern a single battery should be connected to the BAT1 pin. The BAT2 battery pin must be
grounded. When batteries are first connected to one or both of the VBAT pins VCCO will not show the
battery potential until VCCI is applied and removed for the first time.
OPERATION - WRITE PROTECTION PROGRAMMING MODE
When the disable pin is connected to VCCI or VCCO, the DS1610 performs all of the functions described
earlier with the addition of a partition switch which selectively write protects blocks of memory. The state
of the DIS pin is strobed and latched as VCCI crosses the power-fail trip point so that the DS1610
maintains its configuration during power loss. If the strobed value of DIS is a high the internal pulldown
resistor on the DIS pin will be disconnected in the power-fail state to eliminate the possibility of battery
discharge. The register controlling the partition switch is selected by recognition of a specific binary
pattern which is sent on address lines AW -AZ. These address lines are normally the four upper order
address lines being sent to RAM. The pattern is sent by 20 consecutive read cycles with the exact pattern
as shown in Table 1. Pattern matching must be accomplished using read cycles; any write cycles will
reset the pattern matching circuitry. If this pattern is matched perfectly, then the 21st through 24th read
cycle will load the partition switch. Since there are 16 possible write protected partitions, the size of each
partition is determined by the size of the memory. For example, a 128k X 8 memory would be divided
into 16 partitions of 128k/16 or 8k X 8. Each partition is represented by one of the 16 bits contained in the
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DS1610
21st through 24th read cycle as defined by AW through AZ and shown in Table 2. A logical 1 in a bit
location sets that partition to write protect. A logical 0 in a bit location disables write protection. For
example, if during the pattern match sequence bit 22 on address pin AX were a 1, this would cause the
partition register location for partition 5 to be set to a 1. This in turn would cause the DS1610 to inhibit
WEO from going low as WEI goes low whenever AZAYAXAW=0101. Note that while setting the partition
register, data which is being accessed from the RAM should be ignored as the purpose of the 24 read
cycles is to set the partition switch and not for the purpose of accessing data from RAM. Also note that on
initial battery attach the partition register can power-up in any state.
PATTERN MATCH TO WRITE PARTITION REGISTER Table 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AW 1 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 X X X X
AX 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 X X X X
AY 1 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 X X X X
AZ 1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 X X X X
PARTITION REGISTER MAPPING Table 2
Address Bit number in pattern
Partition Number
Pin Match sequence
AW BIT 21
AX BIT 21
AY BIT 21
AZ BIT 21
AW BIT 22
PARTITION 0
PARTITION 1
PARTITION 2
PARTITION 3
PARTITION 4
AX BIT 22
AY BIT 22
AZ BIT 22
AW BIT 23
AX BIT 23
AY BIT 23
AZ BIT 23
PARTITION 5
PARTITION 6
PARTITION 7
PARTITION 8
PARTITION 9
PARTITION 10
PARTITION 11
AW BIT 24
AX BIT 24
AY BIT 24
AZ BIT 24
PARTITION 12
PARTITION 13
PARTITION 14
PARTITION 15
Address State Affected
(AZ AY AX AW)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.5V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
DS1610
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL MIN
TYP
Pin 6 = GND Supply Voltage
Pin 6 = VCCO Supply Voltage
Logic 1 Input
Logic 0 Input
Battery Input
VCCI
VCCI
VIH
VIL
VBAT1,
VBAT2
4.75 5.0
4.5 5.0
2.0
-0.3
2.0
MAX
5.5
5.5
VCC+0.3
+0.8
4.0
(0°C to 70°C)
UNITS NOTES
V1
V1
V1
V1
V 1, 2
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C, VCCI WITHIN DC OPERATING CONDITIONS)
PARAMETER
SYMBOL MIN
TYP MAX
Operating Current
ICC1
5
Standby Current
ICC2
200
Supply Voltage
VCCO
VCC-0.2
Supply Current
ICCO1
150
Input Leakage
IIL -1.0
+1.0
Output Leakage
ILO -1.0
+1.0
VCC Trip Point (TOL=GND)
VCCTP
4.50 4.62 4.75
VCC Trip Point (TOL=VCC)
VCCTP
4.25 4.37 4.50
CEI to CEO Impedance
ZCE
30
DIS Pulldown Resistance
RDIS
50k
250k
PFO , WEO Output @ 2.4V IOH -1.0
PFO , WEO Output @ 0.4V
IOL
4.0
UNITS
mA
µA
V
mA
µA
µA
V
V
ȍ
ȍ
mA
mA
NOTES
3, 14
3, 15
1
4
1, 16
1, 16
5
10, 16
10, 16
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL MIN
CEO Output
VOHL
VBAT-0.2
WEO Output
VOHL
VBAT-0.2
VBAT1or VBAT2 Battery Current
Battery Backup Current @
VCCO = VBAT -0.2V
IBAT
ICCO2
TYP
(0°C to 70°C; VCC<4.5V)
MAX UNITS NOTES
V
V
100 nA 2, 3
150 µA 6, 7, 8
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CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
MIN
TYP
MAX
5
7
DS1610
(tA = 25°C)
UNITS NOTES
pF
pF
(0°C to 70°C; VCCI = 4.75V to 5.50V, TOL= GND)
AC ELECTRICAL CHARACTERISTICS
(VCCI = 4.50V to 5.50V, TOL-VCCO)
PARAMETER
SYMBOL MIN
TYP MAX UNITS NOTES
Address Setup
tAS 0
ns 9
Address Hold
tAH 50
ns 9
Read Recovery
tRR 10
ns 9
CEI , WEI Pulse Width
tCW 75
ns 9
CEI to CEO Falling
tPDF
5 ns 10
Propagation Delay
Later of CEI , WEI to WEO
tPDF
20 ns 10, 11
Falling Propagation Delay
CEI to CEO Rising
tPDR
5 ns 10
Propagation Delay
Earlier of CEI , WEI to WEO
tPDR
5 ns 10, 11
Rising Propagation Delay
Write Recovery
tWR 10
ns 9, 11
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL MIN
Recovery at Power-Up
VCC Slew Rate Power-Down
VCC Slew Rate Power-Down
VCC Slew Rate Power-Up
CEO Pulse Width
tREC
tF
tFB
tF
tWP, tCE
25
300
10
0
WEO Pulse Width
tWP, tCE
(0°C to 70°C; VCC<4.5V)
TYP MAX UNITS NOTES
125 ms
12
µs
µs
µs 13
1.5 µs 7, 8
1.5 µs 7, 8
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