BU2381FV.pdf 데이터시트 (총 5 페이지) - 파일 다운로드 BU2381FV 데이타시트 다운로드

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Multimedia ICs
BU2381FV
Clock generator for digital still camera
BU2381FV
BU2381FV is a high-performance 3-channel PLL IC. PLL circuit generates necessary clocks by inputting standard clocks
of crystal oscillator from outside. Changing a connection of wire can generate any clocks required for any applications of
users. Jitter and S/N characteristic has achieved almost the same high-quality sound and vision as oscillating module
because of optimization of PLL. Frequency can be changed by the internal dividing control.
zApplications
Digital still camera
zFeatures
1) Generate clocks for video output, CDS, USB from standard
clock input
2) No external elements required for PLL
3) Standard clocks apply to two kinds of NTSC/PAL
4) Single power supply of 3.3V operating
5) SSOP-B16 small package
zExternal dimensions (Unit : mm)
5.0±0.2
16 9
18
0.15±0.1
0.65 0.1
0.22±0.1
SSOP-B16
zAbsolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Applied voltage
VDD 0.5 to +7.0
Input voltage
VIN 0.5 to VDD+0.5
Storage temperature range
Power dissipation
Tstg
Pd
30 to +125
450
Derating : 4.5mW/°C for operating above Ta=25°C
An operation is not guaranteed.
Radiation resistance design is not used.
Power dissipation is measured when BU2381FV is placed on the board.
Unit
V
V
°C
mW
zRecommended operating conditions (Ta=25°C)
Parameter
Symbol Min. Typ.
Max.
Supply voltage
VDD 3.0 3.6
Input "H" voltage range
VIH 0.8VDD
VDD
Input "L" voltage range
VIL 0 0.2VDD
Operation temperature range
Topr
5
70
Output maximum load
CL − − 15
Unit
V
V
V
°C
pF
1/5

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zBlock diagram
14.318182MHz
XTAL_IN
XTAL_OUT
XTAL
OSC
CLK2ON
FS1
FS2
FS3
BU2381FV
Data1a
Data1b
Data1c
PLL1 144M
180M 228M
PLL2
192MHz
PLL3
177MHz
1/2
71.877274MHz or 90.314686MHz
or 114.54546MHz
1/2
96.016044MHz
1/2
96.016044MHz
1/4
48.008022MHz
CLK1
CLK2
1 / 10
17.734450MHz
14.318182MHz
REF_CLK
zPin descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin name
REFCLK
VDD
FS3
VSS
XIN
TEST
XOUT
FS2
CLK1OUT
FS1
CLK2ON
VSS
VDD
CLK2OUT
VSS
VDD
Functions
14.3MHz / 17.7MHz clock output
Analog VDD
CLK1, 2 output select with pull up
Analog GND
Standard crystal input
Input for test mode (normally open)
Standard crystal output
CLK1, 2 output select with pull up
71M / 90M / 96M / 114MHz clock output
REFCLK output select with pull up
CLK2 output control with pull up H : enable L : disable
GND for CLK1, 2 clock output and Logic circuit
VDD for CLK1, 2 clock output and Logic circuit
96M / 48M clock output
GND for REFCLK clock output
VDD for REFCLK clock output
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zInput output circuits
Pin No.
Input PIN
3, 8, 10, 11
with pullup
(PIN6 : TESTpin with
pull down)
OUTPUT PIN
1, 9, 14
BU2381FV
Equivalent circuit
To inside IC
From inside IC
Crystal PIN
5, 7
XTALIN
XTALOUT
To inside IC
3/5

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BU2381FV
zElectrical characteristics (Unless specified otherwise Ta=25°C, VCC=3.3V)
Parameter
Symbol
Min.
Typ.
Max. Unit
Conditions
Power supply current IDD 40 50 mA No load
Output frequency
FS2 : H
FS3 : H
CLK1
FS2 : H
FS3 : L
FS2 : L
FS3 : L
FS2 : L
FS3 : H
CLK2
FS2 : L
FS3 : L
FS2, 3 :
HL / LH / HH
REFCLK
FS1 : H
FS1 : L
Duty1 at 100MHz
Fclk1-1
Fclk1-2
Fclk1-3
Fclk1-4
Fclk2-1
Fclk2-2
Fref1-1
Fref1-2
Duty1
−−−
96.016044
Xtal (228 / 17) / 2
71.877274
Xtal (251 / 25) / 2
114.54546 MHz Xtal (224 / 14) / 2
90.314686 MHz Xtal (164 / 12) / 2
96.016044 MHz Xtal (228 / 17) / 2
48.008022 MHz Xtal (228 / 17) / 4
14.318182 MHz Crystal direct output
17.73445 MHz Xtal (706 / 57) / 10
45 50 55 % Measured at 1/2 VDD
Duty2 at 100MHz
Duty2
50
% Measured at 1/2 VDD
Rise time
tr 2.5 nsec Time between 0.2 VDD and 0.8 VDD
Fall time
Period jitter 1σ
tf 2.5 nsec Time between 0.8 VDD and 0.2 VDD
P-J1σ
30
psec 1
Period jitter MIN-MAX P-JMINMAX 180 psec 2
Output Lock time
Tlock
1 msec 3
Note) When input frequency is 14.318182MHz, output frequency is above rated value.
1) Period Jitter 1σ : This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling.
2) Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling.
3) Output Lock time : This value is the time until the output clock gets stable after the power supply voltage leads to 3.0V.
4/5

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zApplication example
REFCLK output
FS3 H or L
0.1µF
FS2 H or L
1
2
3
4
5
6
7
8
BU2381FV
16
0.1µF
15
CLK2 output
14
13
0.1µF
12
CLK2 ON H or L
11
FS1 H or L
10
CLK1 output
9
Note) The BU2381FV is placed on the board normally.
A decoupling capacitor (0.1µF) needs to be placed between pin2 and pin4, pin13 and pin12, pin16 and pin15.
The decoupling capacitor is an close to the above pins as possible.
5/5