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8XC198
COMMERCIAL EXPRESS CHMOS MICROCONTROLLER
8 Kbytes of OTPROM
Y 8 Kbytes of On-Chip OTPROM or ROM
Y 232 Byte Register File
Y Register-to-Register Architecture
Y 28 Interrupt Sources 16 Vectors
Y 1 75 ms 16 x 16 Multiply (16 MHz)
Y 3 0 ms 32 16 Divide (16 MHz)
Y Powerdown and Idle Modes
Y 16-Bit Watchdog Timer
Y 8-Bit External Bus
Y 16 MHz Standard
Y Full Duplex Serial Port
Y High Speed I O Subsystem
Y 16-Bit Timer
Y 16-Bit Counter
Y Pulse-Width-Modulated Output
Y Four 16-Bit Software Timers
Y 10-Bit A D Converter with Sample Hold
Y Extended Temperature Available
The 8XC198 family offers low-cost entry into Intel’s powerful MCS -96 16-bit microcontroller architecture
Intel’s CHMOS process provides a high performance processor along with low power consumption To further
reduce power requirements the processor can be placed into Idle or Powerdown Mode
The 8XC198 is the 8-bit bus version of the 8XC196KB The prefixes mean 80 (ROMless) 83 (ROM) 87 (OTP)
One Time Programmable The ROM and OTP are available in 8 Kbytes
Bit byte word and some 32-bit operations are available on the 8XC198 With a 16 MHz oscillator a 16-bit
addition takes 0 50 ms and the instruction times average 0 37 ms to 1 1 ms in typical applications
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or counter Also provided on-chip are an A D
converter serial port watchdog timer and a pulse-width-modulated output signal
With the commercial (standard) temperature option operational characteristics are guaranteed over the tem-
perature range of 0 C to a70 C Wth the extended temperature range option operational characteristics are
guaranteed over the temperature range of b40 C to a85 C
MCS -96 is a registered trademark of Intel Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
October 1992
Order Number 272034-003

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8XC198
Figure 1 87C198 Block Diagram
272034 – 1
EXTERNAL MEMORY OR I O
INTERNAL ROM EPROM OR
EXTERNAL MEMORY
RESERVED
UPPER 8 INTERRUPT VECTORS
ROM OTP SECURITY KEY
RESERVED
CHIP CONFIGURATION BYTE
RESERVED
LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
PORT 3 AND PORT 4
EXTERNAL MEMORY OR I O
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
0FFFFH
4000H
2080H
2040H
2030H
2020H
2019H
2018H
2014H
2000H
1FFEH
0100H
0000H
272034 – 7
Figure 3 Chip Configuration (2018H)
Figure 2 Memory Map
WARNING
Reserved memory locations must not be written or read The contents and or function of these locations may change with
future revisions of the device Therefore a program that relies on one or more of these locations may not function properly
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8XC198
PACKAGING
The 8XC198 is available in a 52-pin PLCC package and an 80-pin QFP package Contact your local sales
office to determine the exact ordering code for the part desired
Package Designators
N e 52-pin PLCC
S e 80-pin QFP
Thermal Characteristics
Package Type
PLCC
ija
40 C W
QFP
70 C W
ijc
4C W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will
change depending on operating conditions and application See the Intel Packaging Handbook (Order Number
240800) for a description of Intel’s thermal impedance test methodology
272034 – 2
Figure 4 52-Pin PLCC Package
NOTE
The above pinout diagram applies to the OTP (87C198) device The OTP device uses all of the programming pins shown
above The ROM (83C198) device only uses programming pins AINC PALE PMODE n and PROG The ROMless (80C198)
doesn’t use any of the programming pins
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8XC198
NOTE
N C means No Connect (do not connect these pins)
272034 – 4
Figure 5 80-Pin QFP Package
NOTE
The above pinout diagram applies to the OTP (87C198) device The OTP device uses all of the programming pins shown
above The ROM (83C198) device only uses programming pins AINC PALE PMODE n and PROG The ROMless (80C198)
doesn’t use any of the programming pins
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8XC198
PIN DESCRIPTIONS
Symbol
Name and Function
VCC Main supply voltage (5V)
VSS The PLCC package has 5 VSS pins and the QFP package has 12 VSS pins All must be
connected to digital ground
VREF
Reference voltage for the A D converter (5V) VREF is also the supply voltage to the
analog portion of the A D converter and the logic used to read Port 0 Must be
connected for A D and Port 0 to function
ANGND
VPP
XTAL1
Reference ground for the A D converter Must be held at nominally the same potential
as VSS
Programming Voltage Also timing pin for the return from powerdown circuit
Input of the oscillator inverter and of the internal clock generator
XTAL2
Output of the oscillator inverter
RESET
Reset input to and open-drain output from the chip Input low for at least 4 state times to
reset the chip The subsequent low-to-high transition commences the 10-state Reset
Sequence
INST
Output high during an external memory read indicates the read is an instruction fetch
INST is valid throughout the bus cycle INST is activated only during external memory
accesses and output low for a data fetch
EA Input for memory select (External Access) EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM EPROM
EA equal to a TTL-low causes accesses to these locations to be directed to off-chip
memory
ALE ADV
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a latch to demultiplex the address from the address data bus When the pin is
ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during
external memory accesses
RD Read signal output to external memory RD is activated only during external memory
reads
WR Write output to external memory WR will go low for every external write
READY
Ready input to lengthen external memory cycles When the external memory is not
being used READY has no effect Internal control of the number of wait states inserted
into a bus cycle held not ready is available through configuration of CCR
HSI Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and
HSI 3 Two of them (HSI 2 and HSI 3) are shared with the HSO Unit
HSO
Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1
HSO 2 HSO 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the
HSI Unit
Port 0
4-bit high impedance input-only port These pins can be used as digital inputs and or as
analog inputs to the on-chip A D converter These pins set the Programming Mode on
the EPROM device
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