80220.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 80220 데이타시트 다운로드

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www.DataSheet4U.com
80228002/8200/82022211
100BASE-TX/10BASE-T Ethernet
Media Interface Adapter
98184
Features
s Single Chip 100Base-TX / 10Base-T Physical Layer
Solution
s Dual Speed - 100/10 Mbps
s Half And Full Duplex
s MII Interface To Ethernet Controller
s MI Interface For Configuration & Status
s Optional Repeater Interface
s AutoNegotiation: 10/100, Full/Half Duplex
s Meets All Applicable IEEE 802.3, 10Base-T,
100Base-TX Standards
s On Chip Wave Shaping - No External Filters
Required
s Adaptive Equalizer
s Baseline Wander Correction
s Interface to External 100Base-T4 PHY
s LED Outputs
- Link
- Activity
- Collision
- Full Duplex
- 10/100
- User Programmable
s Many User Features And Options
s Few External Components
s Pin configuration
- 44L PLCC - 80220
- 64L LQFP - 80221
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
Description
The 80220/80221 are highly integrated analog interface
IC's for twisted pair Ethernet applications. The 80220/
80221 can be configured for either 100 Mbps (100Base-
TX) or 10 Mbps (10Base-T) Ethernet operation. The
80220 is packaged in a 44L package, while the 80221 is
packaged in a 64L package and contains a few more
features.
The 80220/80221 consist of 4B5B/Manchester encoder/
decoder, scrambler/descrambler, 100Base-TX/10Base-T
twisted pair transmitter with wave shaping and output
driver, 100Base-TX/10Base-T twisted pair receiver with
on chip equalizer and baseline wander correction, clock
and data recovery, AutoNegotiation, controller interface
(MII), and serial port (MI).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters nor-
mally required in 100Base-TX and 10Base-T applications.
The 80220/80221 can automatically configure itself for
100 or 10 Mbps and Full or Half Duplex operation with the
on-chip AutoNegotiation algorithm.
The 80220/80221 can access eleven 16-bit registers though
the Management Interface (MI) serial port. These registers
contain configuration inputs, status outputs, and device
capabilities.
The 80220/80221 are ideal as media interfaces for
100Base-TX/10Base-T adapter cards, motherboards, re-
peaters, switching hubs, and external PHY's.
MD400159/E
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Pin Configuration
PLED2 (MDA2) 7
PLED3 (MDA3) 8
GND3 9
VCC3 10
VCC4 11
MDINT (MDA4) 12
MDC 13
MDIO 14
COL 15
CRS 16
RX_DV 17
80220/80221
80220
TOP VIEW
44L PLCC
39 TRFADJ0
38 TRFADJ1
37 OSCIN
36 GND4
35 TX_EN
34 TX_ER / TXD4
33 TXD3
32 TXD2
31 TXD1
30 TXD0
29 TX_CLK
NC 1
PLED4 2
PLED2 (MDA2) 3
PLED3 (MDA3) 4
NC 5
GND3 6
VCC3 7
VCC4 8
MDINT (MDA4) 9
MDC 10
MDIO 11
COL 12
CRS 13
RX_DV 14
NC 15
NC 16
80221
TOP VIEW
64L LQFP
48 NC
47 NC
46 TRFADJ0
45 TRFADJ1
44 NC
43 NC
42 OSCIN
41 GND4
40 TX_EN
39 TX_ER / TXD4
38 TXD3
37 TXD2
36 TXD1
35 TXD0
34 TX_CLK
33 NC
MD400159/E
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80220 / 80221 TABLE OF CONTENTS
1.0 Pin Description
2.0 Block Diagram
3.0 Functional Description
3.1 General
3.2 Differences between 80220 and 80221
3.3 Controller Interface
3.3.1 General
3.3.2 MII - 100 Mbps
3.3.3 MII - 10 Mbps
3.3.4 FBI - 100 Mbps
3.3.5 Selection of MII or FBI
3.3.6 MII Disable
3.3.7 Receive Output High Impedance Control
3.3.8 TXEN to CRS Loopback Disable
3.4 Encoder
3.4.1 4B5B Encoder - 100 Mbps
3.4.2 Manchester Encoder - 10 Mbps
3.4.3 Encoder Bypass
3.5 Decoder
3.5.1 4B5B Decoder
3.5.2 Manchester Decoder
3.5.3 Decoder Bypass
3.5 Clock and Data Recovery
3.5.1 Clock Recovery - 100 Mbps
3.5.2 Data Recovery - 100 Mbps
3.5.3 Clock Recovery - 10 Mbps
3.5.4 Data Recovery - 10 Mbps
3.6 Scrambler
3.6.1 100 Mbps
3.6.2 10 Mbps
3.6.3 Scrambler Bypass
3.7 Descrambler
3.7.1 100 Mbps
3.7.2 10 Mbps
3.7.3 Descrambler Bypass
3.8 Twisted Pair Transmitter
3.8.1 100 Mbps
3.8.2 10 Mbps
3.8.3 Transmit Level Adjust
3.8.4 Transmit Rise and Fall Time Adjust
3.8.5 STP (150 Ohm) Cable Mode
3.8.6 Transmit Activity Indication
3.8.7 Transmit Disable
3.8.8 Transmit Powerdown
80220/80221
3.9 Twisted Pair Receiver
3.9.1 Receiver - 100 Mbps
3.9.2 Receiver - 10 Mbps
3.9.3 TP Squelch - 100 Mbps
3.9.4 TP Squelch - 10 Mbps
3.9.5 Equalizer Disable
3.9.6 Receive Level Adjust
3.9.7 Receive Activity Indication
3.10 Collision
3.10.1 100 Mbps
3.10.2 10 Mbps
3.10.3 Collision Test
3.10.4 Collision Indication
3.11 Start of Packet
3.11.1 100 Mbps
3.11.2 10 Mbps
3.12 End of Packet
3.12.1 100 Mbps
3.12.2 10 Mbps
3.13 Link Integrity & AutoNegotiation
3.13.1 General
3.13.2 10BaseT Link Integrity Algorithm - 10 Mbps
3.13.3 100BaseTX Link Integrity
Algorithm - 100 Mbps
3.13.4 AutoNegotiation Algorithm
3.13.5 AutoNegotiation Outcome Indication
3.13.6 AutoNegotiation Status
3.13.7 AutoNegotiation Enable
3.13.8 AutoNegotiation Reset
3.13.9 Link Indication
3.13.10 Link Disable
3.13.11 100BaseT4 Capability
3.14 Jabber
3.14.1 100 Mbps
3.14.2 10 Mbps
3.14.3 Jabber Disable
3.15 Receive Polarity Correction
3.15.1 100 Mbps
3.15.2 10 Mbps
3.15.3 Autopolarity Disable
3.16 Full Duplex Mode
3.16.1 100 Mbps
3.16.2 10 Mbps
3.16.3 Full Duplex Indication
3.17 100 / 10 Mbps Selection
3.17.1 General
3.17.2 100 / 10 Mbps Indication
MD400159/E
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80220/80221
80220 / 80221 TABLE OF CONTENTS continued
3.18 Loopback
3.18.1 Internal CRS Loopback
3.18.2 Diagnostic Loopback
3.19 Automatic JAM
3.19.1 100 Mbps
3.19.2 10 Mbps
3.20 Reset
3.21 Powerdown
3.22 Oscillator
3.23 LED Drivers
3.24 100Base-T4 Interface
3.25 Repeater Mode
3.26 MI Serial Port
3.26.1 Signal Description
3.26.2 Timing
3.26.3 Multiple Register Access
3.26.4 Bit Types
3.26.5 Frame Structure
3.26.6 Register Structure
3.26.7 Interrupt
4.0 Register Description
5.0 Application Information
5.1 Example Schematics
5.2 TP Transmit Interface
5.3 TP Receive Interface
5.4 TP Transmit Output Current Set
5.5 Cable Selection
5.6 Transmitter Droop
5.7 MII Controller Interface
5.7.1 General
5.7.2 Clocks
5.7.3 Output Drive
5.7.4 MII Disable
5.7.5 Receive Output Enable
5.8 FBI Controller Interface
5.9 Repeater Applications
5.9.1 MII Based Repeaters
5.9.2 Non-MII Based Repeaters
5.9.3 Clocks
5.10 Serial Port
5.10.1 General
5.10.2 Polling vs. Interrupt
5.10.3 Multiple Register Access
5.10.4 Serial Port Addressing
5.11 Long Cable
5.12 Automatic JAM
5.13 Oscillator
5.14 Programmable LED Drivers
5.15 Power Supply Decoupling
6.0 Specifications
7.0 Ordering Information
7.1 44 Pin PLCC
7.2 64 Pin LQFP
8.0 Package Diagrams
8.1 44 Pin PLCC
8.2 64 Pin LQFP
9.0 Addendum
MD400159/E
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80220/80221
1.0 Pin Description
Pin# Pin
44L 64L Name
28 32 VCC6
24 25 VCC5
11 8 VCC4
10 7 VCC3
1 57 VCC2
44 56 VCC1
I/O Description
Positive Supply. 5 ± 5% Volts
27 31 GND6
23 23 GND5
36 41 GND4
9 6 GND3
4 60 GND2
41 52 GND1
Ground. 0 Volts
42 54 TPO+ O Twisted Pair Transmit Output, Positive.
43 55 TPO -
2 58 TPI+
O Twisted Pair Transmit Output, Negative.
I Twisted Pair Receive Input, Positive.
3 59 TPI -
I Twisted Pair Receive Input, Negative.
40 50 REXT
Transmit Current Set. An external resistor connected between this pin and GND will set the
output current level for the twisted pair outputs.
37 42 OSCIN I Clock Oscillator Input. There must be either a 25 Mhz crystal between this pin and GND or
a 25 Mhz clock applied to this pin. TX_CLK output is generated from this input.
29 34 TX_CLK O
Transmit Clock Output. This controller interface output provides a clock to an external
controller. Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on
rising edges of TX_CLK and OSCIN.
35 40 TX_EN I Transmit Enable Input. This controller interface input has to be asserted active high to
indicate that data on TXD and TX_ER is valid, and it is clocked in on rising edges of TX_CLK
and OSCIN.
33 38 TXD3
32 37 TXD2
31 36 TXD1
30 35 TXD0
I Transmit Data Input. These controller interface inputs contain input nibble data to be
transmitted on the TP outputs, and they are clocked in on rising edges of TX_CLK and OSCIN
when TX_EN is asserted.
34 39 TX_ER / I
TXD4
Transmit Error Input. This controller interface input causes a special pattern to be
transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising
edges of TX_CLK when TX_EN is asserted.
25 26 RX_CLK O
If the device is placed in the Bypass 4B5B Encoder mode, this pin is reconfigured to be the
fifth TXD transmit data input, TXD4.
Receive Clock Output. This controller interface output provides a clock to an external
controller. Receive data on RXD, RX_DV, and RX_ER is clocked out on falling edges of
RX_CLK.
16 13 CRS
O Carrier Sense Output. This controller interface output is asserted active high when valid data
is detected on the receive twisted pair inputs, and it is clocked out on falling edges of RX_CLK.
17 14 RX_DV O Receive Data Valid Output. This controller interface output is asserted active high when valid
decoded data is present on the RXD outputs, and it is clocked out on falling edges of RX_CLK.
19 19 RXD3
20 20 RXD2
21 21 RXD1
22 22 RXD0
O Receive Data Output. These controller interface outputs contain receive nibble data from
the TP input, and they are clocked out on falling edges of RX_CLK.
MD400159/E
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